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gatecatrobtaylor
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Add standalone export of SPI peripheral (#19)
* Add standalone export of SPI peripheral Signed-off-by: gatecat <[email protected]> * Update dependencies Signed-off-by: gatecat <[email protected]> --------- Signed-off-by: gatecat <[email protected]>
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my_design/ips/spi.py

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@@ -188,3 +188,11 @@ def elaborate(self, platform):
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if __name__ == '__main__':
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from amaranth.back import verilog
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from pathlib import Path
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spi = SPIPeripheral(name="spi")
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Path("build/export/ips").mkdir(parents=True, exist_ok=True)
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with open("build/export/ips/spi_peripheral.v", "w") as f:
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f.write(verilog.convert(spi, name="spi_peripheral"))

pdm.lock

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