|
7 | 7 | import re |
8 | 8 | import subprocess |
9 | 9 |
|
10 | | -from dataclasses import dataclass |
11 | 10 | from pprint import pformat |
12 | 11 | from typing import TYPE_CHECKING, List, Generic |
13 | 12 |
|
14 | 13 | from amaranth import Module, Signal, ClockDomain, ClockSignal, ResetSignal, unsigned |
15 | | -from amaranth.lib import wiring, io, data |
| 14 | +from amaranth.lib import io, data |
16 | 15 | from amaranth.lib.cdc import FFSynchronizer |
17 | | -from amaranth.lib.wiring import Component, In |
18 | 16 | from amaranth.back import rtlil #type: ignore[reportAttributeAccessIssue] |
19 | 17 | from amaranth.hdl import Fragment |
20 | 18 | from amaranth.hdl._ir import PortDirection |
|
31 | 29 | logger = logging.getLogger(__name__) |
32 | 30 |
|
33 | 31 |
|
34 | | -def make_hashable(cls): |
35 | | - def __hash__(self): |
36 | | - return hash(id(self)) |
37 | | - |
38 | | - def __eq__(self, obj): |
39 | | - return id(self) == id(obj) |
40 | | - |
41 | | - cls.__hash__ = __hash__ |
42 | | - cls.__eq__ = __eq__ |
43 | | - return cls |
44 | | - |
45 | | - |
46 | | -HeartbeatSignature = wiring.Signature({"heartbeat_i": In(1)}) |
47 | | - |
48 | | - |
49 | | -@make_hashable |
50 | | -@dataclass |
51 | | -class Heartbeat(Component): |
52 | | - clock_domain: str = "sync" |
53 | | - counter_size: int = 23 |
54 | | - name: str = "heartbeat" |
55 | | - |
56 | | - def __init__(self, ports): |
57 | | - super().__init__(HeartbeatSignature) |
58 | | - self.ports = ports |
59 | | - |
60 | | - def elaborate(self, platform): |
61 | | - m = Module() |
62 | | - # Heartbeat LED (to confirm clock/reset alive) |
63 | | - heartbeat_ctr = Signal(self.counter_size) |
64 | | - getattr(m.d, self.clock_domain).__iadd__(heartbeat_ctr.eq(heartbeat_ctr + 1)) |
65 | | - |
66 | | - heartbeat_buffer = io.Buffer(io.Direction.Output, self.ports.heartbeat) |
67 | | - m.submodules.heartbeat_buffer = heartbeat_buffer |
68 | | - m.d.comb += heartbeat_buffer.o.eq(heartbeat_ctr[-1]) # type: ignore |
69 | | - return m |
70 | | - |
71 | | - |
72 | 32 | class SiliconPlatformPort(io.PortLike, Generic[Pin]): |
73 | 33 | def __init__(self, |
74 | 34 | name: str, |
|
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