Fix output ports to not have output enable signals (_oe)

- Removed _oe signal for output ports
- Updated IOBuffer to only set oe for bidirectional ports
- Updated wire method to handle cases where _oe is None
- Updated tests to match the new behavior

🤖 Generated with [Claude Code](https://claude.ai/code)

Co-Authored-By: Claude <[email protected]>

Author: robtaylor

chipflow_lib/platforms/silicon.py

@@ -90,18 +90,19 @@ def __init__(self,
             else:
                 self._oe = Signal(1, name=f"{component}_{name}__oe", init=-1)
         elif self._direction is io.Direction.Output:
-            # Always create an _oe for output ports
-            self._oe = Signal(1, name=f"{component}_{name}__oe", init=-1)
+            # Output ports don't need an _oe
+            self._oe = None
 
         logger.debug(f"Created SiliconPlatformPort {name}, width={len(port.pins)},dir{self._direction}")
 
     def wire(self, m: Module, interface: PureInterface):
         assert self._direction == interface.signature.direction
         if hasattr(interface, 'i'):
             m.d.comb += interface.i.eq(self.i)
-        for d in ['o', 'oe']:
-            if hasattr(interface, d):
-                m.d.comb += getattr(self, d).eq(getattr(interface, d))
+        if hasattr(interface, 'o'):
+            m.d.comb += self.o.eq(interface.o)
+        if hasattr(interface, 'oe') and self._oe is not None:
+            m.d.comb += self.oe.eq(interface.oe)
 
     @property
 
@@ -121,7 +122,7 @@ def o(self):
     @property
     def oe(self):
         if self._oe is None:
-            raise AttributeError("SiliconPlatformPort with input direction does not have an "
+            raise AttributeError("SiliconPlatformPort with output or input direction does not have an "
                                "output enable signal")
         return self._oe
 
@@ -216,7 +217,9 @@ def elaborate(self, platform):
             m.d.comb += i_inv.eq(self.port.i)
         if self.direction in (io.Direction.Output, io.Direction.Bidir):
             m.d.comb += self.port.o.eq(o_inv)
-            m.d.comb += self.port.oe.eq(self.oe)
+            # Only set oe for bidirectional ports
+            if self.direction is io.Direction.Bidir:
+                m.d.comb += self.port.oe.eq(self.oe)
 
         return m