Namespace simulation models

Author: robtaylor

chipflow_lib/common/sim/main.cc.jinja

@@ -12,6 +12,7 @@
 
 using namespace cxxrtl::time_literals;
 using namespace cxxrtl_design;
+using namespace chipflow;
 
 int main(int argc, char **argv) {
     p_sim__top top;

chipflow_lib/common/sim/models.cc

@@ -9,7 +9,7 @@
 #include <unordered_map>
 #include "models.h"
 
-namespace cxxrtl_design {
+namespace chipflow {
 
 // Helper functions
 
@@ -134,8 +134,10 @@ void close_event_log() {
     }
 }
 
+namespace models {
+
 // SPI flash
-void spiflash_model::load_data(const std::string &filename, unsigned offset) {
+void spiflash::load_data(const std::string &filename, unsigned offset) {
     std::ifstream in(filename, std::ifstream::binary);
     if (offset >= data.size()) {
         throw std::out_of_range("flash: offset beyond end");
@@ -145,7 +147,7 @@ void spiflash_model::load_data(const std::string &filename, unsigned offset) {
     }
     in.read(reinterpret_cast<char*>(data.data() + offset), (data.size() - offset));
 }
-void spiflash_model::step(unsigned timestamp) {
+void spiflash::step(unsigned timestamp) {
     auto process_byte = [&]() {
         s.out_buffer = 0;
         if (s.byte_count == 0) {
@@ -221,7 +223,7 @@ void spiflash_model::step(unsigned timestamp) {
 
 // UART
 
-void uart_model::step(unsigned timestamp) {
+void uart::step(unsigned timestamp) {
 
     for (auto action : get_pending_actions(name)) {
         if (action.event == "tx") {
@@ -275,7 +277,7 @@ void uart_model::step(unsigned timestamp) {
 }
 
 // Generic SPI model
-void spi_model::step(unsigned timestamp) {
+void spi::step(unsigned timestamp) {
     for (auto action : get_pending_actions(name)) {
         if (action.event == "set_data") {
             s.out_buffer = s.send_data = uint32_t(action.payload);
@@ -308,7 +310,7 @@ void spi_model::step(unsigned timestamp) {
 }
 
 // Generic I2C model
-void i2c_model::step(unsigned timestamp) {
+void i2c::step(unsigned timestamp) {
     bool sda = !bool(sda_oe), scl = !bool(scl_oe);
 
     for (auto action : get_pending_actions(name)) {
@@ -370,4 +372,5 @@ void i2c_model::step(unsigned timestamp) {
     scl_i.set(scl);
 }
 
-}
+} //chipflow::models
+} //chipflow

chipflow_lib/common/sim/models.h

@@ -10,7 +10,7 @@
 #include "vendor/nlohmann/json.hpp"
 
 
-namespace cxxrtl_design {
+namespace chipflow {
 
 using namespace cxxrtl;
 
@@ -30,9 +30,12 @@ void log_event(unsigned timestamp, const std::string &peripheral, const std::str
 std::vector<action> get_pending_actions(const std::string &peripheral);
 void close_event_log();
 
-struct spiflash_model {
+namespace models {
+
+
+struct spiflash {
     std::string name;
-    spiflash_model(const std::string &name, const value<1> &clk, const value<1> &csn, const value<4> &d_o, const value<4> &d_oe, value<4> &d_i) : 
+    spiflash(const std::string &name, const value<1> &clk, const value<1> &csn, const value<4> &d_o, const value<4> &d_oe, value<4> &d_i) : 
         name(name), clk(clk), csn(csn), d_o(d_o), d_oe(d_oe), d_i(d_i) {
         data.resize(16*1024*1024);
         std::fill(data.begin(), data.end(), 0xFF); // flash starting value
@@ -61,9 +64,9 @@ struct spiflash_model {
     } s;
 };
 
-struct uart_model {
+struct uart {
     std::string name;
-    uart_model(const std::string &name, const value<1> &tx, value<1> &rx, unsigned baud_div = 25000000/115200) : name(name), tx(tx), rx(rx), baud_div(baud_div) {};
+    uart(const std::string &name, const value<1> &tx, value<1> &rx, unsigned baud_div = 25000000/115200) : name(name), tx(tx), rx(rx), baud_div(baud_div) {};
 
     void step(unsigned timestamp);
 private:
@@ -83,10 +86,10 @@ struct uart_model {
 };
 
 template<int pin_count>
-struct gpio_model {
+struct gpio {
     std::string name;
 
-    gpio_model(const std::string &name, const value<pin_count> &o, const value<pin_count> &oe, value<pin_count> &i) : name(name), o(o), oe(oe), i(i) {};
+    gpio(const std::string &name, const value<pin_count> &o, const value<pin_count> &oe, value<pin_count> &i) : name(name), o(o), oe(oe), i(i) {};
 
     void step(unsigned timestamp);
 
@@ -104,7 +107,7 @@ struct gpio_model {
 
 // GPIO
 template<int pin_count>
-void gpio_model<pin_count>::step(unsigned timestamp) {
+void gpio<pin_count>::step(unsigned timestamp) {
     uint32_t o_value = o.template get<uint32_t>();
     uint32_t oe_value = oe.template get<uint32_t>();
 
@@ -135,9 +138,9 @@ void gpio_model<pin_count>::step(unsigned timestamp) {
     s.oe_last = oe_value;
 }
 
-struct spi_model {
+struct spi {
     std::string name;
-    spi_model(const std::string &name, const value<1> &clk, const value<1> &copi, value<1> &cipo, const value<1> &csn) : 
+    spi(const std::string &name, const value<1> &clk, const value<1> &copi, value<1> &cipo, const value<1> &csn) : 
         name(name), clk(clk), csn(csn), copi(copi), cipo(cipo) {
     };
 
@@ -159,9 +162,9 @@ struct spi_model {
     } s;
 };
 
-struct i2c_model {
+struct i2c {
     std::string name;
-    i2c_model(const std::string &name, const value<1> &scl_o, const value<1> &scl_oe, value<1> &scl_i, const value<1> &sda_o, const value<1> &sda_oe, value<1> &sda_i)  : name(name), sda_oe(sda_oe), sda_i(sda_i), scl_oe(scl_oe), scl_i(scl_i) {};
+    i2c(const std::string &name, const value<1> &scl_o, const value<1> &scl_oe, value<1> &scl_i, const value<1> &sda_o, const value<1> &sda_oe, value<1> &sda_i)  : name(name), sda_oe(sda_oe), sda_i(sda_i), scl_oe(scl_oe), scl_i(scl_i) {};
 
     void step(unsigned timestamp);
 private:
@@ -184,6 +187,7 @@ struct i2c_model {
 };
 
 
-}
+} //chipflow::simulation
+} //chipflow
 
 #endif

chipflow_lib/platforms/_annotate.py

@@ -1,8 +1,7 @@
 from types import MethodType
 import pydantic
-from amaranth.lib import meta
-from typing import Any, Annotated, NamedTuple, Self, TypeVar
-from typing_extensions import TypedDict, is_typeddict
+from typing import TypeVar
+from typing_extensions import is_typeddict
 _T_TypedDict = TypeVar('_T_TypedDict')
 
 def amaranth_annotate(modeltype: type['_T_TypedDict'], schema_id: str, member='__chipflow_annotation__', decorate_object = False):

chipflow_lib/platforms/_signatures.py

@@ -7,7 +7,6 @@
 from amaranth.lib import wiring
 from amaranth.lib.wiring import Out
 
-from .. import ChipFlowError
 from ._utils import InputIOSignature, OutputIOSignature, BidirIOSignature, IOModelOptions, _chipflow_schema_uri
 from ._annotate import amaranth_annotate
 

chipflow_lib/platforms/_utils.py

@@ -13,18 +13,17 @@
 from enum import Enum, IntEnum, StrEnum, auto
 from math import ceil, floor
 from typing import (
-    Any, Annotated, NamedTuple, Self, Type,
-    TYPE_CHECKING
+    Any, Annotated, NamedTuple, Self, TYPE_CHECKING
 )
 from typing_extensions import (
     TypedDict, Unpack, NotRequired
 )
 
 
-from amaranth.lib import wiring, io, meta
+from amaranth.lib import wiring, io
 from amaranth.lib.wiring import In, Out
 from pydantic import (
-        ConfigDict, TypeAdapter, PlainSerializer,
+        ConfigDict, PlainSerializer,
         WrapValidator
         )
 

chipflow_lib/platforms/silicon.py

@@ -14,7 +14,7 @@
 from amaranth import Module, Signal, ClockDomain, ClockSignal, ResetSignal, unsigned
 from amaranth.lib import wiring, io, data
 from amaranth.lib.cdc import FFSynchronizer
-from amaranth.lib.wiring import Component, In, PureInterface
+from amaranth.lib.wiring import Component, In
 from amaranth.back import rtlil  #type: ignore[reportAttributeAccessIssue]
 from amaranth.hdl import Fragment
 from amaranth.hdl._ir import PortDirection
@@ -333,16 +333,6 @@ def __init__(self,
         self._gpio_analog_sel = None # analog mux select
         self._gpio_analog_pol = None # analog mux select
 
-    def wire(self, m: Module, interface: PureInterface):
-        super().wire(m, interface)
-
-        # wire up drive mode bits
-        bit = 0
-        for i in self._dms:
-            m.d.comb += self._dm0[bit].eq(i[0]) # type: ignore
-            m.d.comb += self._dm1[bit].eq(i[1]) # type: ignore
-            m.d.comb += self._dm2[bit].eq(i[2]) # type: ignore
-
     def instantiate_toplevel(self):
         ports = super().instantiate_toplevel()
         for s, d in self._signals:
@@ -354,6 +344,8 @@ def instantiate_toplevel(self):
     def wire_up(self, m, wire):
         super().wire_up(m, wire)
 
+        # wire up drive mode bits
+
         if hasattr(wire, 'drive_mode'):
             m.d.comb += self.drive_mode.eq(wire.drive_mode)
 

chipflow_lib/platforms/sim.py

@@ -4,16 +4,14 @@
 import os
 import sys
 
-from collections import defaultdict
 from dataclasses import dataclass
 from enum import StrEnum
 from pathlib import Path
 from pprint import pformat
 from typing import Dict, List, Optional, Type
 
-from amaranth import Value, ValueCastable, Module, Signal, ClockSignal, ResetSignal, ClockDomain
-from amaranth.lib import io, meta, wiring
-from amaranth.lib.wiring import In, Out
+from amaranth import Module, ClockSignal, ResetSignal, ClockDomain
+from amaranth.lib import io, wiring
 from amaranth.back import rtlil  # type: ignore[reportAttributeAccessIssue]
 from amaranth.hdl._ir import PortDirection
 from amaranth.lib.cdc import FFSynchronizer
@@ -46,6 +44,7 @@ class SimModel:
         capabilities: List of capabilities of the model.
     """
     name: str
+    namespace: str
     signature: Type[wiring.Signature]
     capabilities: Optional[List[SimModelCapability]] = None
 
@@ -103,9 +102,6 @@ class BasicCxxBuilder(BaseModel):
     def model_post_init(self, *args, **kwargs):
         self._table = { getattr(m.signature,'__chipflow_uid__'): m for m in self.models }
 
-    def uid_to_c(self, uid: str) -> str:
-        return uid.replace('.','__')
-
     def instantiate_model(self, interface: str, sim_interface: SimInterface, interface_desc: Interface, ports: Dict[str, io.SimulationPort]) -> str:
         uid = sim_interface['uid']
         parameters = sim_interface['parameters']
@@ -120,11 +116,10 @@ def instantiate_model(self, interface: str, sim_interface: SimInterface, interfa
         sig_names = [ path for path, _, _ in members ]
         port_names = { n: interface_desc[n].port_name for n in interface_desc.keys()}
 
-        identifier_uid = self.uid_to_c(uid)
         names = [f"\\io${port_names[str(n)]}${d}" for n,d in sig_names]
         params = [f"top.{cxxrtlmangle(n)}" for n in names]
 
-        cpp_class = model.name
+        cpp_class = f"{model.namespace}::{model.name}"
         if len(parameters):
             template_params = []
             for p,v in parameters:
@@ -146,11 +141,11 @@ def find_builder(builders: List[BasicCxxBuilder], sim_interface: SimInterface):
 
 _COMMON_BUILDER = BasicCxxBuilder(
     models=[
-        SimModel('spi_model', SPISignature),
-        SimModel('spiflash_model', QSPIFlashSignature,  [SimModelCapability.LOAD_DATA]),
-        SimModel('uart_model', UARTSignature),
-        SimModel('i2c_model', I2CSignature),
-        SimModel('gpio_model', GPIOSignature),
+        SimModel('spi', 'chipflow::models', SPISignature),
+        SimModel('spiflash', 'chipflow::models', QSPIFlashSignature,  [SimModelCapability.LOAD_DATA]),
+        SimModel('uart', 'chipflow::models', UARTSignature),
+        SimModel('i2c', 'chipflow::models', I2CSignature),
+        SimModel('gpio', 'chipflow::models', GPIOSignature),
         ],
     cpp_files=[ Path('{COMMON_DIR}', 'models.cc') ],
     hpp_files=[ Path('models.h') ],