including sim_build../Makefile

johnymil-chipflow · robtaylor · commit 84f4db76fc70 · 2024-09-14T16:09:20.000+02:00
diff --git a/pyuvm_verif/Makefile b/pyuvm_verif/Makefile
@@ -1,6 +1,6 @@
 CWD=$(shell pwd)
 SIM=verilator
-VERILOG_SOURCES=$(wildcard $(CWD)/verilog/*.v)
+VERILOG_SOURCES=$(wildcard $(CWD)/*/*.v)
 .PHONY: print_vars
 
 ifeq ($(ARG),SPI)
