wip

Author: robtaylor

chipflow_lib/__init__.py

@@ -1,59 +1,2 @@
-# SPDX-License-Identifier: BSD-2-Clause
-from dataclasses import dataclass
-from typing import Dict, Union, Any
-
-from amaranth import (
-        Module,
-        Elaboratable,
-        Signal,
-        ClockDomain,
-        ClockSignal,
-        ResetSignal
-        )
-
-from amaranth.lib import io
-from amaranth.lib.cdc import FFSynchronizer
-from amaranth.lib.wiring import Component
-from .platforms.iostream import PortSignature, IOShape
-
 class ChipFlowError(Exception):
-    pass
-
-def make_hashable(cls):
-    def __hash__(self):
-        return hash(id(self))
-
-    def __eq__(self, obj):
-        return id(self) == id(obj)
-
-    cls.__hash__ = __hash__
-    cls.__eq__ = __eq__
-    return cls
-
-
-@make_hashable
-@dataclass
-class Heartbeat(Component):
-    clock_domain: str = "sync"
-    counter_size: int = 23
-    name: str = "heartbeat"
-
-    def pins():
-        return IOShape({
-            'heartbeat': {'heartbeat': ('o', 1)}
-            })
-
-    def __init__(self):
-        super().__init__(PortSignature({}))
-        self._ioshape = self.__class__.pins()
-    
-    def elaborate(self, platform):
-        m = Module()
-        # Heartbeat LED (to confirm clock/reset alive)
-        heartbeat_ctr = Signal(self.counter_size)
-        getattr(m.d, self.clock_domain).__iadd__(heartbeat_ctr.eq(heartbeat_ctr + 1))
-
-        heartbeat_buffer = io.Buffer("o", self.ports.heartbeat)
-        m.submodules.heartbeat_buffer = heartbeat_buffer
-        m.d.comb += heartbeat_buffer.o.eq(heartbeat_ctr[-1])
-        return m
+    pass

chipflow_lib/cli.py

@@ -174,6 +174,8 @@ def run(argv=sys.argv[1:]):
             raise ChipFlowError(f"Encountered error while building CLI argument parser for "
                                 f"step `{step_name}`")
 
+    pins = parser.add_subparsers("pins")
+    lock = lock.add_subparsers("lock")
     args = parser.parse_args(argv)
     try:
         steps[args.step].run_cli(args)

chipflow_lib/errors.py

@@ -0,0 +1,3 @@
+class ChipFlowError(Exception):
+    pass
+

chipflow_lib/pin_lock.py

@@ -1,16 +1,12 @@
 import json
-import logging
 import re
-import sys
 
-from amaranth import Shape
+from pprint import pprint
 from pathlib import Path
-from pprint import pformat
 
-from chipflow_lib.platforms.iostream import PORT_LAYOUT_SCHEMA
+from amaranth import Shape
 from chipflow_lib.cli import _parse_config, _get_cls_by_reference
-
-logger = logging.getLogger(__name__)
+from chipflow_lib.platforms import PACKAGE_DEFINITIONS
 
 def has_consecutive_numbers(lst):
     if not lst:
@@ -69,114 +65,111 @@ def coalesce_triples(sig: dict) -> None:
     if sig['type'] == 'port':
         pass
 
-def count_pins(port):
-    width = 0
-    for _, v in port.items():
-        if type(v) is dict:
+def count_pins(member):
+    if member['type'] == 'interface':
+        width = 0
+        for _, v in member['members'].items():
             width += count_pins(v)
+        return width
+    elif member['type'] == 'port':
+        return member['width']
+
+def allocate_pins(name, member, pins, pin_map):
+    print(f"allocate_pins: {pins}")
+    if member['type'] == 'interface':
+        for k, v in member['members'].items():
+            n = '_'.join([name,k])
+            pins = allocate_pins(n, v, pins, pin_map)
+        return pins
+    elif member['type'] == 'port':
+        name = name
+        width = member['width']
+        if width == 1:
+            pin_map[name] = {'pin':pins[0], 'type':member['dir']}
         else:
-            width += v[1]
-    return width
-
-
-def allocate_pins(name, port, pins):
-    pin_map = {}
-    logger.debug(f"allocate_pins: name={name}, port={port}, pins={pins}")
-    for k, v in port.items():
-        n = '_'.join([name,k])
-        logger.debug(f"{k},{v},{n}")
-        if type(v) is dict:
-            _map, pins = allocate_pins(n, v, pins)
-            pin_map |= _map
-            logger.debug(f"{pin_map},{_map}")
+            pin_map[name] = {'start':pins[0], 
+                             'end':pins[width-1], 
+                             'type':member['dir']}
+        return pins[width:]
+
+
+def check_pins(name, member, old_map, new_map):
+    if member['type'] == 'interface':
+        for k, v in member['members'].items():
+            n = '_'.join([name,k])
+            check_pins(n, v, old_map, new_map)
+    elif member['type'] == 'port':
+        width = member['width']
+        if width == 1:
+            assert 'pin' in old_map[name]
         else:
-            direction, width = v
+            assert 'start' in old_map[name]
+            assert 'end' in old_map[name]
+            assert old_map[name]['end'] - old_map[name]['start'] + 1 == width
+        new_map[name] = old_map[name]
+
+def connect_pins(pin_map):
+    for k,v in interfaces.items():
+        if member['type'] == 'interface':
+            for k, v in member['members'].items():
+                n = '_'.join([name,k])
+                check_pins(n, v, old_map, new_map)
+        elif member['type'] == 'port':
+            width = member['width']
             if width == 1:
-                pin_map[n] = {'pin':pins[0], 'type':direction}
+                assert 'pin' in old_map[name]
             else:
-                pin_map[n] = {'start':pins[0], 
-                                'end':pins[width-1], 
-                                'type':direction}
-            logger.debug(f"pin_map[{n}]={pin_map[n]}")
-            pins = pins[width:]
-    return pin_map, pins
-
-
-def assign_pins(ports, old_lock, unallocated):
-    old_ports = old_lock["ports"] if "ports" in old_lock else {}
-    old_map = old_lock["map"]["ports"] if "map" in old_lock else {}
-    pin_map = {}
-
-    # we try to keep pins together for each port
-    for k,v in ports.items():
-        logger.debug(f"Port {k}:\n{pformat(v)}")
-        width = count_pins(v)
-        logger.debug(f"member {k} total width = {width}")
-
-        if k in old_ports:
-            logger.debug(f"{k} already has pins defined")
-            if width != count_pins(old_ports[k]):
-                raise Exception("Port {k} has changed size. Use -c to allocate new pins non-contigously")
-            _map = old_map[k]
-            old_pins = [v['pin'] for v in old_map[k].values()]
-            logger.debug("old pins = {old_pins}")
-            unallocated = sorted(list(set(unallocated) - set(old_pins)))
-        else:
-            pins = find_consecutive_sequence(unallocated, width)
-            logger.debug(f"allocated range: {pins}")
-            if pins is None:
-                raise Exception(f"Error allocating pins for {k},{v} in {ports}")
-
-            
-            newpins = unallocated[pins]
-            unallocated[pins] = []
-            _map,_ = allocate_pins(k, v, newpins)
-        
-        pin_map[k] = _map
-    return pin_map
+                assert 'start' in old_map[name]
+                assert 'end' in old_map[name]
+                assert old_map[name]['end'] - old_map[name]['start'] + 1 == width
+            new_map[name] = old_map[name]
 
 
-logging.basicConfig(level=logging.DEBUG, stream=sys.stdout)
 config = _parse_config()
 used_pins = set()
 pin_map = {}
 lockfile = Path('pins.lock')
 if lockfile.exists():
     with open(lockfile) as f:
         old_lock = json.load(f)
-        old_map = old_lock["map"]
+        old_interfaces = old_lock['interfaces']
+        old_map = old_lock['map']
 else:
-    old_lock = {}
     old_map = {}
+    old_interfaces = {}
+
+package = config["chipflow"]["silicon"]["padring"]
 
-for d, default in [("pads", "i"), ("power","pwr")]:
-    logger.debug(f"Checking [chipflow.silicon.{d}]:")
-    pin_map[d] = {}
+if package not in PACKAGE_DEFINITIONS:
+    print(f"Package '{package} is unknown")
+
+for d in ("pads", "power"):
+    print(f"Checking [chipflow.silicon.{d}]:")
     for k, v in config["chipflow"]["silicon"][d].items():
-        pin = int(v['loc'])
+        pin = v['loc']
         used_pins.add(pin)
-        if d in old_map and k in old_map[d] and old_map[d][k]['pin'] != pin:
+        if k in old_map and old_map[k]['pin'] != pin:
             print(f"chipflow.toml conflicts with pins.lock: "
-                  f"{k} had pin {old_map[d][k]}, now {pin}.")
+                  f"{k} had pin {old_map[k]}, now {pin}.")
             exit(1)
-        pin_map[d][k] = {
+        pin_map[k] = {
             'pin': pin,
             'type': v['type'] if 'type' in v else None}
 
 
-logger.info(f'Pins in use:\n{pformat(sorted(used_pins))}')
+print(f'Pins in use: {sorted(used_pins)}')
 
-unallocated = sorted(set(range(144)) - used_pins)
+unallocated = sorted(PACKAGE_DEFINITIONS[package] - used_pins)
 
-ports = {}
+interfaces = {}
 top_components = config["chipflow"]["top"].items()
 component_configs = {}
 top = {}
 
 for name, conf in top_components:
     if '.' in name:
         assert conf is dict
-        logger.debug("Config found for {name}")
+        print("Config found for {name}")
         component_configs[name.split('.')[0]] = conf
 
 for name, ref in top_components:
@@ -186,16 +179,38 @@ def assign_pins(ports, old_lock, unallocated):
     else:
         top[name] = cls()
     metadata = top[name].metadata.as_json()
-    logger.debug(f"{name}.metadata = {metadata}")
-    ports |= metadata['interface']['annotations'][PORT_LAYOUT_SCHEMA]['ports']
-
-logger.debug(f"All ports: {list(ports.keys())}")
-
-pin_map["ports"] = assign_pins(ports, old_lock, unallocated)
+    interfaces |= metadata['interface']['members']
+
+print(f"All interfaces: {interfaces.keys()}")
+pin_map_interfaces = {}
+
+# we try to keep pins together for each interface
+for k,v in interfaces.items():
+    print(f"Interface {k}:")
+    pprint(v)
+    width = count_pins(v)
+    print(f"member {k} total width = {width}")
+    pins = find_consecutive_sequence(unallocated, width)
+    print(f"allocated range: {pins}")
+    if pins is None:
+        print("ERROR")
+    if k in old_interfaces:
+        if old_interfaces[k]['start'] != pins.start or \
+           old_interfaces[k]['end'] != pins.stop:
+            # TODO: option to allocate new pins nonconsecutively
+            print("top level interface has changed size")
+            exit(1)
+        check_pins(k, v, old_map, pin_map)
+        pin_map_interfaces[k] = {'top': True, 'start':pins.start, 'end':pins.stop}
+    else:
+        pin_map_interfaces[k] = {'top': True, 'start':pins.start, 'end':pins.stop}
+        newpins = unallocated[pins]
+        unallocated[pins] = []
+        allocate_pins(k, v, newpins, pin_map)
 
 with open('pins.lock', 'w') as f:
-    newlock = {'map': pin_map,
-               'ports': ports}
+    newlock = {'interfaces': pin_map_interfaces,
+               'map': pin_map}
 
     json.dump(newlock, f, indent=2, sort_keys=True)
 #