Add comprehensive test suite for improved code coverage

- Added tests for core modules (__init__, cli, config, errors)
- Added tests for silicon platform components (SiliconPlatformPort, buffers, Heartbeat)
- Added tests for platform utilities (schema utils, package definitions, PortMap)
- Added basic tests for SimPlatform
- Improved overall test coverage significantly
- Removed old Heartbeat implementation

🤖 Generated with [Claude Code](https://claude.ai/code)

Co-Authored-By: Claude <[email protected]>

merge 3f35493

Author: robtaylor

chipflow_lib/platforms/silicon.py

@@ -5,13 +5,11 @@
 import os
 import subprocess
 
-from dataclasses import dataclass
-
 from amaranth import Module, Signal, Cat, ClockDomain, ClockSignal, ResetSignal
 
-from amaranth.lib import wiring, io
+from amaranth.lib import io
 from amaranth.lib.cdc import FFSynchronizer
-from amaranth.lib.wiring import Component, In, PureInterface
+from amaranth.lib.wiring import PureInterface
 
 from amaranth.back import rtlil
 from amaranth.hdl import Fragment
@@ -25,44 +23,6 @@
 logger = logging.getLogger(__name__)
 
 
-def make_hashable(cls):
-    def __hash__(self):
-        return hash(id(self))
-
-    def __eq__(self, obj):
-        return id(self) == id(obj)
-
-    cls.__hash__ = __hash__
-    cls.__eq__ = __eq__
-    return cls
-
-
-HeartbeatSignature = wiring.Signature({"heartbeat_i": In(1)})
-
-
-@make_hashable
-@dataclass
-class Heartbeat(Component):
-    clock_domain: str = "sync"
-    counter_size: int = 23
-    name: str = "heartbeat"
-
-    def __init__(self, ports):
-        super().__init__(HeartbeatSignature)
-        self.ports = ports
-
-    def elaborate(self, platform):
-        m = Module()
-        # Heartbeat LED (to confirm clock/reset alive)
-        heartbeat_ctr = Signal(self.counter_size)
-        getattr(m.d, self.clock_domain).__iadd__(heartbeat_ctr.eq(heartbeat_ctr + 1))
-
-        heartbeat_buffer = io.Buffer("o", self.ports.heartbeat)
-        m.submodules.heartbeat_buffer = heartbeat_buffer
-        m.d.comb += heartbeat_buffer.o.eq(heartbeat_ctr[-1])
-        return m
-
-
 class SiliconPlatformPort(io.PortLike):
     def __init__(self,
                  component: str,

tests/test_config.py

@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: BSD-2-Clause
+import os
+import unittest
+
+from chipflow_lib.config import get_dir_models, get_dir_software
+
+
+class TestConfig(unittest.TestCase):
+    def test_get_dir_models(self):
+        """Test get_dir_models returns the correct path"""
+        # Since we can't predict the absolute path, we'll check that it ends correctly
+        models_dir = get_dir_models()
+        self.assertTrue(models_dir.endswith("/chipflow_lib/models"))
+        self.assertTrue(os.path.isdir(models_dir))
+
+    def test_get_dir_software(self):
+        """Test get_dir_software returns the correct path"""
+        # Since we can't predict the absolute path, we'll check that it ends correctly
+        software_dir = get_dir_software()
+        self.assertTrue(software_dir.endswith("/chipflow_lib/software"))
+        self.assertTrue(os.path.isdir(software_dir))

tests/test_errors.py

@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: BSD-2-Clause
+import unittest
+
+from chipflow_lib.errors import ChipFlowError
+
+
+class TestErrors(unittest.TestCase):
+    def test_chipflow_error(self):
+        """Test that ChipFlowError can be instantiated and raised"""
+        # Test instantiation
+        error = ChipFlowError("Test error message")
+        self.assertEqual(str(error), "Test error message")
+
+        # Test raising
+        with self.assertRaises(ChipFlowError) as cm:
+            raise ChipFlowError("Test raised error")
+
+        self.assertEqual(str(cm.exception), "Test raised error")
+
+        # Test inheritance
+        self.assertTrue(issubclass(ChipFlowError, Exception))

tests/test_silicon_platform_build.py

@@ -0,0 +1,144 @@
+# amaranth: UnusedElaboratable=no
+# SPDX-License-Identifier: BSD-2-Clause
+
+import os
+import unittest
+from unittest import mock
+
+import tomli
+from amaranth import Module, Signal
+
+from chipflow_lib import ChipFlowError
+
+
+class TestSiliconPlatformBuild(unittest.TestCase):
+    def setUp(self):
+        os.environ["CHIPFLOW_ROOT"] = os.path.dirname(os.path.dirname(__file__))
+        current_dir = os.path.dirname(__file__)
+        customer_config = f"{current_dir}/fixtures/mock.toml"
+        with open(customer_config, "rb") as f:
+            self.config = tomli.load(f)
+
+    def test_silicon_platform_init(self):
+        """Test SiliconPlatform initialization"""
+        # Import here to avoid issues during test collection
+        from chipflow_lib.platforms.silicon import SiliconPlatform
+
+        # Create platform
+        platform = SiliconPlatform(self.config)
+
+        # Check initialization
+        self.assertEqual(platform._config, self.config)
+        self.assertEqual(platform._ports, {})
+        self.assertEqual(platform._files, {})
+
+    def test_request_valid_port(self):
+        """Test request method with a valid port name"""
+        # Import here to avoid issues during test collection
+        from chipflow_lib.platforms.silicon import SiliconPlatform
+
+        # Create platform
+        platform = SiliconPlatform(self.config)
+
+        # Mock ports dictionary
+        platform._ports = {
+            "test_port": "port_value"
+        }
+
+        # Request the port
+        result = platform.request("test_port")
+
+        # Check result
+        self.assertEqual(result, "port_value")
+
+    def test_request_invalid_name(self):
+        """Test request method with an invalid port name (contains $)"""
+        # Import here to avoid issues during test collection
+        from chipflow_lib.platforms.silicon import SiliconPlatform
+
+        # Create platform
+        platform = SiliconPlatform(self.config)
+
+        # Request a port with $ in the name
+        with self.assertRaises(NameError) as cm:
+            platform.request("invalid$port")
+
+        self.assertIn("Reserved character `$` used in pad name", str(cm.exception))
+
+    def test_request_nonexistent_port(self):
+        """Test request method with a port name that doesn't exist"""
+        # Import here to avoid issues during test collection
+        from chipflow_lib.platforms.silicon import SiliconPlatform
+
+        # Create platform
+        platform = SiliconPlatform(self.config)
+
+        # Mock ports dictionary
+        platform._ports = {
+            "test_port": "port_value"
+        }
+
+        # Request a non-existent port
+        with self.assertRaises(NameError) as cm:
+            platform.request("nonexistent_port")
+
+        self.assertIn("Pad `nonexistent_port` is not present in the pin lock", str(cm.exception))
+
+    def test_add_file(self):
+        """Test add_file method"""
+        # Import here to avoid issues during test collection
+        from chipflow_lib.platforms.silicon import SiliconPlatform
+
+        # Create platform
+        platform = SiliconPlatform(self.config)
+
+        # Test with string content
+        platform.add_file("test1.v", "module test1();endmodule")
+        self.assertIn("test1.v", platform._files)
+        self.assertEqual(platform._files["test1.v"], b"module test1();endmodule")
+
+        # Test with file-like object
+        file_obj = mock.Mock()
+        file_obj.read.return_value = "module test2();endmodule"
+        platform.add_file("test2.v", file_obj)
+        self.assertIn("test2.v", platform._files)
+        self.assertEqual(platform._files["test2.v"], b"module test2();endmodule")
+
+        # Test with bytes content
+        platform.add_file("test3.v", b"module test3();endmodule")
+        self.assertIn("test3.v", platform._files)
+        self.assertEqual(platform._files["test3.v"], b"module test3();endmodule")
+
+    @mock.patch("chipflow_lib.platforms.silicon.rtlil.convert_fragment")
+    @mock.patch("chipflow_lib.platforms.silicon.SiliconPlatform._prepare")
+    @mock.patch("os.makedirs")
+    @mock.patch("builtins.open", mock.mock_open())
+    @mock.patch("subprocess.check_call")
+    def test_build_mocked(self, mock_check_call, mock_makedirs, mock_prepare, mock_convert_fragment):
+        """Test build method with mocks"""
+        # Import here to avoid issues during test collection
+        from chipflow_lib.platforms.silicon import SiliconPlatform
+
+        # Set up mocks
+        mock_prepare.return_value = "fragment"
+        mock_convert_fragment.return_value = ("rtlil_text", None)
+
+        # Create platform
+        platform = SiliconPlatform(self.config)
+
+        # Add some files
+        platform._files = {
+            "test.v": b"module test();endmodule",
+        }
+
+        # Create a test module
+        m = Module()
+
+        # Call build
+        platform.build(m, name="test_top")
+
+        # Check that the required methods were called
+        mock_prepare.assert_called_once_with(m, "test_top")
+        mock_convert_fragment.assert_called_once_with("fragment", "test_top")
+        mock_makedirs.assert_called_once()
+        mock_check_call.assert_called_once()

tests/test_sim_platform.py

@@ -0,0 +1,72 @@
+# amaranth: UnusedElaboratable=no
+# SPDX-License-Identifier: BSD-2-Clause
+
+import os
+import unittest
+from unittest import mock
+
+import tomli
+from amaranth import Module, Signal, Cat, ClockDomain
+from amaranth.lib import io
+
+from chipflow_lib import ChipFlowError
+
+
+class TestSimPlatform(unittest.TestCase):
+    def setUp(self):
+        """Set up test environment"""
+        # Set up environment variable
+        self.original_chipflow_root = os.environ.get("CHIPFLOW_ROOT")
+        os.environ["CHIPFLOW_ROOT"] = os.path.dirname(os.path.dirname(__file__))
+
+        # Load config for use in tests
+        current_dir = os.path.dirname(__file__)
+        customer_config = f"{current_dir}/fixtures/mock.toml"
+        with open(customer_config, "rb") as f:
+            self.config = tomli.load(f)
+
+    def tearDown(self):
+        """Clean up environment"""
+        if self.original_chipflow_root:
+            os.environ["CHIPFLOW_ROOT"] = self.original_chipflow_root
+        else:
+            os.environ.pop("CHIPFLOW_ROOT", None)
+
+    def test_sim_platform_init(self):
+        """Test SimPlatform initialization"""
+        # Import here to avoid issues during test collection
+        from chipflow_lib.platforms.sim import SimPlatform
+
+        # Create platform
+        platform = SimPlatform()
+
+        # Check initialization
+        self.assertEqual(platform.build_dir, os.path.join(os.environ['CHIPFLOW_ROOT'], 'build', 'sim'))
+        self.assertEqual(platform.extra_files, {})
+        self.assertEqual(platform.sim_boxes, {})
+
+        # Check signals
+        self.assertIsInstance(platform.clk, Signal)
+        self.assertIsInstance(platform.rst, Signal)
+        self.assertIsInstance(platform.buttons, Signal)
+        self.assertEqual(len(platform.buttons), 2)
+
+    def test_add_file(self):
+        """Test add_file method"""
+        # Import here to avoid issues during test collection
+        from chipflow_lib.platforms.sim import SimPlatform
+
+        # Create platform
+        platform = SimPlatform()
+
+        # Test with string content
+        platform.add_file("test.v", "module test(); endmodule")
+        self.assertIn("test.v", platform.extra_files)
+        self.assertEqual(platform.extra_files["test.v"], "module test(); endmodule")
+
+        # Test with file-like object
+        file_obj = mock.Mock()
+        file_obj.read.return_value = "module test2(); endmodule"
+        platform.add_file("test2.v", file_obj)
+        self.assertIn("test2.v", platform.extra_files)
+        self.assertEqual(platform.extra_files["test2.v"], "module test2(); endmodule")