When port is not using ie, it should be connected to oe *inverted*

Author: robtaylor

chipflow_lib/platforms/silicon.py

@@ -146,7 +146,7 @@ def wire_up(self, m, wire):
         if hasattr(wire, 'ie'):
             m.d.comb += self.ie.eq(wire.ie)
         elif hasattr(wire, 'oe'):
-            m.d.comb += self.ie.eq(wire.oe)
+            m.d.comb += self.ie.eq(~wire.oe)
 
 
     @property