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Remove unused Heartbeat component
1 parent f075225 commit ba4a001

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2 files changed

+1
-78
lines changed

2 files changed

+1
-78
lines changed

chipflow_lib/platforms/silicon.py

Lines changed: 1 addition & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -7,14 +7,12 @@
77
import re
88
import subprocess
99

10-
from dataclasses import dataclass
1110
from pprint import pformat
1211
from typing import TYPE_CHECKING, List, Generic
1312

1413
from amaranth import Module, Signal, ClockDomain, ClockSignal, ResetSignal, unsigned
15-
from amaranth.lib import wiring, io, data
14+
from amaranth.lib import io, data
1615
from amaranth.lib.cdc import FFSynchronizer
17-
from amaranth.lib.wiring import Component, In
1816
from amaranth.back import rtlil #type: ignore[reportAttributeAccessIssue]
1917
from amaranth.hdl import Fragment
2018
from amaranth.hdl._ir import PortDirection
@@ -31,44 +29,6 @@
3129
logger = logging.getLogger(__name__)
3230

3331

34-
def make_hashable(cls):
35-
def __hash__(self):
36-
return hash(id(self))
37-
38-
def __eq__(self, obj):
39-
return id(self) == id(obj)
40-
41-
cls.__hash__ = __hash__
42-
cls.__eq__ = __eq__
43-
return cls
44-
45-
46-
HeartbeatSignature = wiring.Signature({"heartbeat_i": In(1)})
47-
48-
49-
@make_hashable
50-
@dataclass
51-
class Heartbeat(Component):
52-
clock_domain: str = "sync"
53-
counter_size: int = 23
54-
name: str = "heartbeat"
55-
56-
def __init__(self, ports):
57-
super().__init__(HeartbeatSignature)
58-
self.ports = ports
59-
60-
def elaborate(self, platform):
61-
m = Module()
62-
# Heartbeat LED (to confirm clock/reset alive)
63-
heartbeat_ctr = Signal(self.counter_size)
64-
getattr(m.d, self.clock_domain).__iadd__(heartbeat_ctr.eq(heartbeat_ctr + 1))
65-
66-
heartbeat_buffer = io.Buffer(io.Direction.Output, self.ports.heartbeat)
67-
m.submodules.heartbeat_buffer = heartbeat_buffer
68-
m.d.comb += heartbeat_buffer.o.eq(heartbeat_ctr[-1]) # type: ignore
69-
return m
70-
71-
7232
class SiliconPlatformPort(io.PortLike, Generic[Pin]):
7333
def __init__(self,
7434
name: str,

tests/test_steps_silicon.py

Lines changed: 0 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -739,40 +739,3 @@ def test_elaborate_no_heartbeat(self, mock_top_components, mock_platform_class):
739739

740740
# Verify heartbeat was not requested
741741
platform.request.assert_not_called()
742-
743-
@mock.patch("chipflow_lib.platforms.silicon.io.Buffer")
744-
@mock.patch("chipflow_lib.steps.silicon.Module")
745-
@mock.patch("chipflow_lib.platforms.silicon.Heartbeat")
746-
@mock.patch("chipflow_lib.steps.silicon.top_components")
747-
def test_heartbeat(self, mock_top_components, mock_module, mock_heartbeat_class, mock_io_buffer):
748-
"""Test that Heartbeat class gets used properly when debug.heartbeat is True"""
749-
# Import Heartbeat class to make sure it's loaded and used
750-
751-
# Create a mock Heartbeat instance
752-
mock_heartbeat = mock.MagicMock()
753-
mock_heartbeat_class.return_value = mock_heartbeat
754-
755-
# Create a mock platform with a heartbeat port
756-
platform = mock.MagicMock()
757-
platform.pinlock.port_map.ports = {}
758-
platform.ports = {
759-
"heartbeat": mock.MagicMock()
760-
}
761-
platform.request.return_value = platform.ports["heartbeat"]
762-
763-
# Create a mock for top_components
764-
mock_top_components.return_value = {}
765-
766-
# Create and elaborate SiliconTop with heartbeat
767-
config_obj = Config.model_validate(self.config)
768-
top = SiliconTop(config_obj)
769-
result = top.elaborate(platform)
770-
771-
# Verify platform.request was called with "heartbeat"
772-
platform.request.assert_called_with("heartbeat")
773-
774-
# Use the result to ensure the module doesn't trigger UnusedElaboratable
775-
self.assertIsNotNone(result)
776-
777-
# We don't need to test config_no_heartbeat in this test
778-
# The test_elaborate_no_heartbeat already does that

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