sim interface annotation working

Author: robtaylor

chipflow_lib/_signatures.py

@@ -0,0 +1,74 @@
+#undef NDEBUG
+
+#include <cxxrtl/cxxrtl.h>
+#include <cxxrtl/cxxrtl_server.h>
+#include "sim_soc.h"
+{% for include in includes %}
+#include "{{include}}"
+{% endfor %}
+
+#include <fstream>
+#include <filesystem>
+
+using namespace cxxrtl::time_literals;
+using namespace cxxrtl_design;
+
+int main(int argc, char **argv) {
+    p_sim__top top;
+
+    {% for initialiser in initialisers %}
+    {{initialiser}};
+    {% endfor %}
+
+    cxxrtl::agent agent(cxxrtl::spool("spool.bin"), top);
+    if (getenv("DEBUG")) // can also be done when a condition is violated, etc
+        std::cerr << "Waiting for debugger on " << agent.start_debugging() << std::endl;
+
+    open_event_log(BUILD_DIR "/sim/events.json");
+    open_input_commands(PROJECT_ROOT "/design/tests/input.json");
+
+    unsigned timestamp = 0;
+    auto tick = [&]() {
+        {% for interface in interfaces %}
+        {{interface}}.step(timestamp);
+        {% endfor %}
+
+        // FIXME: Currently we tick all clocks together, this need fixing..
+        {% for clock in clocks %}
+        top.{{clock}}.set(false);
+        {% endfor %}
+        agent.step();
+        agent.advance(1_us);
+        ++timestamp;
+
+        {% for clock in clocks %}
+        top.{{clock}}.set(true);
+        {% endfor %}
+        agent.step();
+        agent.advance(1_us);
+        ++timestamp;
+
+        // if (timestamp == 10)
+        //     agent.breakpoint(CXXRTL_LOCATION);
+    };
+
+    flash.load_data(BUILD_DIR "/software/software.bin", 0x00100000U);
+    agent.step();
+    agent.advance(1_us);
+
+    {% for reset in resets %}
+    top.{{reset}}.set(false);
+    {% endfor %}
+
+    tick();
+
+    {% for reset in resets %}
+    top.{{reset}}.set(true);
+    {% endfor %}
+
+    for (int i = 0; i < 3000000; i++)
+        tick();
+
+    close_event_log();
+    return 0;
+}

chipflow_lib/common/sim/main.cc.jinja

@@ -127,7 +127,7 @@ struct spi_model {
 
 struct i2c_model {
     std::string name;
-    i2c_model(const std::string &name, const value<1> &sda_oe, value<1> &sda_i, const value<1> &scl_oe, value<1> &scl_i) : name(name), sda_oe(sda_oe), sda_i(sda_i), scl_oe(scl_oe), scl_i(scl_i) {};
+    i2c_model(const std::string &name, const value<1> &sda_o, const value<1> &sda_oe, value<1> &sda_i, const value<1> &scl_o, const value<1> &scl_oe, value<1> &scl_i) : name(name), sda_oe(sda_oe), sda_i(sda_i), scl_oe(scl_oe), scl_i(scl_i) {};
 
     void step(unsigned timestamp);
 private:

chipflow_lib/common/sim/models.h

@@ -14,11 +14,13 @@
         )
 from ._packages import PACKAGE_DEFINITIONS
 from ._sky130 import Sky130DriveMode
+from ._signatures import JTAGSignature, SPISignature, I2CSignature, UARTSignature, GPIOSignature, QSPIFlashSignature
 
 __all__ = ['IO_ANNOTATION_SCHEMA', 'IOSignature',
            'IOModel', 'IOModelOptions', 'IOTripPoint',
            'OutputIOSignature', 'InputIOSignature', 'BidirIOSignature',
            'SiliconPlatformPort', 'SiliconPlatform',
            'SimPlatform',
+           'JTAGSignature', 'SPISignature', 'I2CSignature', 'UARTSignature', 'GPIOSignature',
            'Sky130DriveMode',
            'PACKAGE_DEFINITIONS']

chipflow_lib/platforms/__init__.py

@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: BSD-2-Clause
+
+from typing_extensions import Unpack, TypedDict
+
+from amaranth.lib import wiring
+from amaranth.lib.wiring import Out
+
+from ._utils import InputIOSignature, OutputIOSignature, BidirIOSignature, IOModelOptions, _chipflow_schema_uri, amaranth_annotate
+
+SIM_ANNOTATION_SCHEMA = str(_chipflow_schema_uri("sim-interface", 0))
+
+class SimInterface(TypedDict):
+    name: str
+    parameters: dict
+
+
+def sim_annotate(klass):
+    original_init_subclass = klass.__init_subclass__
+
+    def new_init_subclass(cls, /, **kwargs):
+        original_init = cls.__init__
+        def new_init(self,*args, **kwargs):
+            original_init(self, *args, **kwargs)
+            self._model = {
+                 "name": cls.__name__,
+                 "parameters": self._get_sim_parameters(),
+                 }
+
+        if original_init_subclass:
+            original_init_subclass(**kwargs)
+        cls.__init__ = new_init
+
+    dec = amaranth_annotate(SimInterface, SIM_ANNOTATION_SCHEMA)
+    klass = dec(klass)
+    klass.__init_subclass__ = classmethod(new_init_subclass)
+    klass._get_sim_parameters = lambda self: {}
+    return klass
+
+
+@sim_annotate
+class SimulatableSignature(wiring.Signature):
+    ...
+
+class JTAGSignature(SimulatableSignature):
+    def __init__(self, **kwargs: Unpack[IOModelOptions]):
+        super().__init__({
+        "trst": Out(InputIOSignature(1)),
+        "tck": Out(InputIOSignature(1)),
+        "tms": Out(InputIOSignature(1)),
+        "tdi": Out(InputIOSignature(1)),
+        "tdo": Out(OutputIOSignature(1)),
+    })
+
+
+class SPISignature(SimulatableSignature):
+    def __init__(self, **kwargs: Unpack[IOModelOptions]):
+        super().__init__({
+            "sck": Out(OutputIOSignature(1)),
+            "copi": Out(OutputIOSignature(1)),
+            "cipo": Out(InputIOSignature(1)),
+            "csn": Out(OutputIOSignature(1)),
+        })
+
+class QSPIFlashSignature(SimulatableSignature):
+    def __init__(self, **kwargs: Unpack[IOModelOptions]):
+        super().__init__({
+            "clk": Out(OutputIOSignature(1)),
+            "csn": Out(OutputIOSignature(1)),
+            "d": Out(BidirIOSignature(4, individual_oe=True)),
+        })
+
+class UARTSignature(SimulatableSignature):
+    def __init__(self, **kwargs: Unpack[IOModelOptions]):
+        super().__init__({
+            "tx": Out(OutputIOSignature(1)),
+            "rx": Out(InputIOSignature(1)),
+        })
+
+class I2CSignature(SimulatableSignature):
+    def __init__(self, **kwargs: Unpack[IOModelOptions]):
+        super().__init__({
+        "scl": Out(BidirIOSignature(1)),
+        "sda": Out(BidirIOSignature(1))
+    })
+
+class GPIOSignature(SimulatableSignature):
+    def __init__(self, pin_count=1, **kwargs: Unpack[IOModelOptions]):
+        if pin_count > 32:
+            raise ValueError(f"Pin pin_count must be lesser than or equal to 32, not {pin_count}")
+        self._pin_count = pin_count
+        kwargs['individual_oe'] = True
+        super().__init__({
+            "gpio": Out(BidirIOSignature(pin_count, **kwargs))
+            })
+    def _get_sim_parameters(self):
+        return {'pin_count': self._pin_count}
+
+    def __repr__(self) -> str:
+        return f"GPIOSignature(pin_count={self._pin_count}, {dict(self.members.items())})"

chipflow_lib/platforms/_signatures.py

@@ -130,12 +130,13 @@ class IOModel(IOModelOptions):
     width: int
     direction: Annotated[io.Direction, PlainSerializer(lambda x: x.value)]
 
-def amaranth_annotate(model: Type[TypedDict], schema_id: str):
+def amaranth_annotate(modeltype: Type[TypedDict], schema_id: str):
+    PydanticModel = TypeAdapter(modeltype)
+
     def annotation_schema():
         class Model(pydantic.BaseModel):
-            data_td: model
+            data_td: modeltype
 
-        PydanticModel = TypeAdapter(model)
         schema = PydanticModel.json_schema()
         schema['$schema'] = "https://json-schema.org/draft/2020-12/schema"
         schema['$id'] = schema_id
@@ -145,21 +146,19 @@ class Annotation(meta.Annotation):
         "Generated annotation class"
         schema = annotation_schema()
 
-        def __init__(self, model:IOModel):
+        def __init__(self, model: modeltype):
             self._model = model
 
         @property
         def origin(self):  # type: ignore
             return self._model
 
         def as_json(self):  # type: ignore
-            return TypeAdapter(IOModel).dump_python(self._model)
+            return PydanticModel.dump_python(self._model)
 
     def annotations(self, *args):  # type: ignore
         annotations = wiring.Signature.annotations(self, *args)  # type: ignore
-        print(f"annotating {self} with {self._model}")
         annotation = Annotation(self._model)
-        print(f"returning {annotations + (annotation,)}")
         return annotations + (annotation,)  # type: ignore
 
     def decorator(klass):
@@ -386,17 +385,17 @@ def _group_consecutive_items(ordering: PinList, lst: PinList) -> OrderedDict[int
     last = lst[0]
     current_group = [last]
 
-    logger.debug(f"_group_consecutive_items starting with {current_group}")
+    #logger.debug(f"_group_consecutive_items starting with {current_group}")
 
     for item in lst[1:]:
         idx = ordering.index(last)
         next = ordering[idx + 1] if idx < len(ordering) - 1 else None
-        logger.debug(f"inspecting {item}, index {idx}, next {next}")
+        #logger.debug(f"inspecting {item}, index {idx}, next {next}")
         if item == next:
             current_group.append(item)
-            logger.debug("found consecutive, adding to current group")
+            #logger.debug("found consecutive, adding to current group")
         else:
-            logger.debug("found nonconsecutive, creating new group")
+            #logger.debug("found nonconsecutive, creating new group")
             grouped.append(current_group)
             current_group = [item]
         last = item