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After discussion, remove oe_n and ie_n, handle in backend
1 parent b94f9be commit c6c730b

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+21
-34
lines changed

1 file changed

+21
-34
lines changed

chipflow_lib/platforms/silicon.py

Lines changed: 21 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -74,13 +74,14 @@ def __init__(self,
7474
name: str,
7575
port_desc: PortDesc):
7676
self._port_desc = port_desc
77+
width = port_desc.iomodel['width']
7778
if 'invert' in port_desc.iomodel:
7879
if isinstance(port_desc.iomodel['invert'], bool):
79-
self._invert = [port_desc.iomodel['invert']]*port_desc.iomodel['width']
80+
self._invert = [port_desc.iomodel['invert']] * width
8081
else:
8182
self._invert = port_desc.iomodel['invert']
8283
else:
83-
self._invert = [False]*port_desc.iomodel['width']
84+
self._invert = [False]*width
8485

8586
self._name = name
8687

@@ -92,16 +93,16 @@ def __init__(self,
9293

9394
# Create signals based on direction
9495
if self.direction in (io.Direction.Input, io.Direction.Bidir):
95-
self._i = Signal(self._port_desc.width, name=f"{self._name}$i")
96-
self._ie = Signal(self._port_desc.width, name=f"{self._name}$inp_dis")
96+
self._i = Signal(width, name=f"{self._name}$i")
97+
self._ie = Signal(width, name=f"{self._name}$ie")
9798
if self.direction in (io.Direction.Output, io.Direction.Bidir):
98-
self._o = Signal(self._port_desc.width, name=f"{self._name}$o")
99+
self._o = Signal(width, name=f"{self._name}$o")
99100

100101
# the oe signals that get wired out to iocells. Always one per io.
101102
init_oe = -1
102103
if 'init_oe' in port_desc.iomodel and port_desc.iomodel['init_oe']:
103104
init_oe = port_desc.iomodel['init_oe']
104-
self._oes = Signal(self._port_desc.width, name=f"{self._name}$oe", init=init_oe)
105+
self._oes = Signal(width, name=f"{self._name}$oe", init=init_oe)
105106

106107
# the oe on the user side.
107108
if "individual_oe" not in self.iomodel or not self.iomodel["individual_oe"]:
@@ -193,6 +194,10 @@ def ie(self):
193194
def direction(self):
194195
return self._port_desc.iomodel['direction']
195196

197+
@property
198+
def width(self):
199+
return self._port_desc.iomodel['width']
200+
196201
@property
197202
def invert(self):
198203
return self._invert
@@ -272,17 +277,6 @@ def __init__(self,
272277
# keep a list of signals we create
273278
self._signals = []
274279

275-
# Now create the signals for ``gpio_oeb`` (``oe_n``), ``gpio_inp_dis`` (``ie_n``)
276-
self._oe_n = None
277-
278-
if self._oe is not None:
279-
self._oe_n = Signal(self._oe.shape().width, name=f"{self._name}$oeb")
280-
self._signals.append((self._oe_n, PortDirection.Output))
281-
282-
if self._ie is not None:
283-
self._ie_n = Signal(self._ie.shape().width, name=f"{self._name}$inp_dis")
284-
self._signals.append((self._ie_n, PortDirection.Output))
285-
286280
# Port Configuration
287281
# Input voltage trip level
288282
if self.direction in (io.Direction.Input, io.Direction.Bidir):
@@ -296,9 +290,9 @@ def __init__(self,
296290
else:
297291
ib_mode_init = vtrip_init = 0
298292

299-
self._ib_mode_sel = Signal(self._i.shape().width, name=f"{self._name}$ib_mode_sel", init=ib_mode_init)
293+
self._ib_mode_sel = Signal(self.width, name=f"{self._name}$ib_mode_sel", init=ib_mode_init)
300294
self._signals.append((self._ib_mode_sel, PortDirection.Output))
301-
self._vtrip_sel = Signal(self._i.shape().width, name=f"{self._name}$vtrip_sel", init=vtrip_init)
295+
self._vtrip_sel = Signal(self.width, name=f"{self._name}$vtrip_sel", init=vtrip_init)
302296
self._signals.append((self._vtrip_sel, PortDirection.Output))
303297

304298
# Drive mode
@@ -309,13 +303,14 @@ def __init__(self,
309303
dm = Sky130DriveMode(port_desc.iomodel['drive_mode'])
310304
else:
311305
dm = Sky130DriveMode.STRONG_UP_STRONG_DOWN
312-
dm_init = Value.cast(__class__._DriveMode_map[dm])
313-
dms_shape = data.ArrayLayout(unsigned(3), self._o.shape().width)
314-
self._dms = Signal(dms_shape, name=f"{self._name}$dms", init=[dm_init]*self._o.shape().width)
315-
316-
self._dm0 = Signal(self._o.shape(), name=f"{self._name}$dm0", init=dm_init[0])
317-
self._dm1 = Signal(self._o.shape(), name=f"{self._name}$dm1", init=dm_init[1])
318-
self._dm2 = Signal(self._o.shape(), name=f"{self._name}$dm2", init=dm_init[2])
306+
dm_init = __class__._DriveMode_map[dm]
307+
dm_init_bits = [ int(b) for b in f"{dm_init:b}"]
308+
dms_shape = data.ArrayLayout(unsigned(3), self.width)
309+
self._dms = Signal(dms_shape, name=f"{self._name}$dms", init=[dm_init]*self.width)
310+
311+
self._dm0 = Signal(self._o.shape(), name=f"{self._name}$dm0", init=dm_init_bits[0])
312+
self._dm1 = Signal(self._o.shape(), name=f"{self._name}$dm1", init=dm_init_bits[1])
313+
self._dm2 = Signal(self._o.shape(), name=f"{self._name}$dm2", init=dm_init_bits[2])
319314
self._signals.append((self._dm0, PortDirection.Output)) #type: ignore
320315
self._signals.append((self._dm1, PortDirection.Output)) #type: ignore
321316
self._signals.append((self._dm2, PortDirection.Output)) #type: ignore
@@ -348,14 +343,6 @@ def instantiate_toplevel(self):
348343

349344
def wire_up(self, m, wire):
350345
super().wire_up(m, wire)
351-
# wire up oe_n = ~oe
352-
if self._oe is not None:
353-
assert self._oe_n is not None
354-
m.d.comb += self._oe_n.eq(~self._oe)
355-
356-
if self._ie is not None:
357-
assert self._ie_n is not None
358-
m.d.comb += self._ie_n.eq(~self._ie)
359346

360347
if hasattr(wire, 'drive_mode'):
361348
m.d.comb += self.drive_mode.eq(wire.drive_mode)

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