Fix test configs with required fields and valid process values

Author: robtaylor

tests/test_init.py

@@ -4,6 +4,7 @@
 import unittest
 import tempfile
 from unittest import mock
+from pathlib import Path
 
 import jsonschema
 import pytest
@@ -135,5 +136,5 @@ def test_parse_config(self, mock_parse_config_file, mock_ensure_chipflow_root):
         config = _parse_config()
 
         mock_ensure_chipflow_root.assert_called_once()
-        mock_parse_config_file.assert_called_once_with("/mock/chipflow/root/chipflow.toml")
+        mock_parse_config_file.assert_called_once_with(Path("/mock/chipflow/root/chipflow.toml"))
         self.assertEqual(config, {"chipflow": {"test": "value"}})

tests/test_pin_lock.py

@@ -223,7 +223,11 @@ def test_lock_pins_new_lockfile(self, mock_lock_file, mock_package_defs,
         # Mock config
         mock_config = {
             "chipflow": {
+                "steps": {
+                    "silicon": "chipflow_lib.steps.silicon:SiliconStep"
+                },
                 "silicon": {
+                    "process": "ihp_sg13g2",
                     "package": "cf20",
                     "pads": {
                         "clk": {"type": "clock", "loc": "1"},
@@ -339,7 +343,11 @@ def test_lock_pins_with_existing_lockfile(self, mock_lock_file, mock_package_def
         # Mock config
         mock_config = {
             "chipflow": {
+                "steps": {
+                    "silicon": "chipflow_lib.steps.silicon:SiliconStep"
+                },
                 "silicon": {
+                    "process": "ihp_sg13g2",
                     "package": "cf20",
                     "pads": {
                         "clk": {"type": "clock", "loc": "1"},
@@ -452,7 +460,11 @@ def __init__(self):
         # Mock config
         mock_config = {
             "chipflow": {
+                "steps": {
+                    "silicon": "chipflow_lib.steps.silicon:SiliconStep"
+                },
                 "silicon": {
+                    "process": "ihp_sg13g2",
                     "package": "cf20",
                     "pads": {
                         "clk": {"type": "clock", "loc": "1"},  # This will be checked by check_pad
@@ -523,7 +535,11 @@ def test_lock_pins_reuse_existing_ports(self, mock_lock_file, mock_package_defs,
         # Mock config
         mock_config = {
             "chipflow": {
+                "steps": {
+                    "silicon": "chipflow_lib.steps.silicon:SiliconStep"
+                },
                 "silicon": {
+                    "process": "ihp_sg13g2",
                     "package": "cf20",
                     "pads": {},
                     "power": {}