Clean up a bit - move unfinished docs away for now

Author: robtaylor

docs/advanced-configuration.rst

@@ -18,7 +18,7 @@ ChipFlow supports multiple clock domains in your design:
    [chipflow.clocks]
    # Default clock for the design
    default = "sys_clk"
-   
+
    # Additional clock domains
    pll = "pll_clk"
    fast = "fast_clk"
@@ -42,11 +42,11 @@ ChipFlow provides debugging options for silicon designs:
    [chipflow.silicon.debug]
    # Heartbeat LED to verify clock/reset functionality
    heartbeat = true
-   
+
    # Internal logic analyzer
    logic_analyzer = true
    logic_analyzer_depth = 1024
-   
+
    # JTAG debug access
    jtag = true
 
@@ -60,7 +60,7 @@ To prevent pin assignments from changing accidentally, ChipFlow supports a pin l
    [chipflow.pin_lock]
    # Enable pin locking
    enabled = true
-   
+
    # Lock file path (relative to project root)
    file = "pins.lock"
 
@@ -76,10 +76,10 @@ For silicon designs, you can specify resource constraints:
    [chipflow.silicon.constraints]
    # Maximum die area in mm²
    max_area = 1.0
-   
+
    # Maximum power budget in mW
    max_power = 100
-   
+
    # Target clock frequency in MHz
    target_frequency = 100
 
@@ -93,7 +93,7 @@ You can specify custom top-level components for your design:
    [chipflow.top]
    # Main SoC component
    soc = "my_design.components:MySoC"
-   
+
    # Additional top-level components
    uart = "my_design.peripherals:UART"
    spi = "my_design.peripherals:SPI"
@@ -113,7 +113,7 @@ FPGA Board Configuration
    [chipflow.board]
    # Target FPGA board
    target = "ulx3s"
-   
+
    # Board-specific options
    [chipflow.board.options]
    size = "85k"  # FPGA size
@@ -148,7 +148,7 @@ ChipFlow can integrate with external dependencies:
      "github.com/chipflow/[email protected]",
      "github.com/chipflow/[email protected]"
    ]
-   
+
    # External library paths
    [chipflow.deps.libs]
    amaranth_cores = "amaranth_cores"
@@ -164,13 +164,13 @@ For more complex testing setups:
    [chipflow.sim]
    # Testbench implementation
    testbench = "my_design.tb:TestBench"
-   
+
    # Custom simulation flags
    [chipflow.sim.options]
    trace_all = true
    cycles = 10000
    seed = 12345
-   
+
    # Test vectors
    [chipflow.sim.test_vectors]
    path = "test_vectors.json"
@@ -186,13 +186,13 @@ To generate custom documentation for your design:
    [chipflow.docs]
    # Documentation output directory
    output = "docs/build"
-   
+
    # Block diagram generation
    block_diagram = true
-   
+
    # Custom templates
    template_dir = "docs/templates"
-   
+
    # Additional documentation files
    extra_files = [
      "docs/architecture.md",
@@ -204,12 +204,10 @@ Environment Variables
 
 Several environment variables can be used to customize ChipFlow's behavior:
 
-- ``CHIPFLOW_ROOT``: Root directory of your project
-- ``CHIPFLOW_API_KEY_ID``: API key ID for ChipFlow services
-- ``CHIPFLOW_API_KEY_SECRET``: API key secret for ChipFlow services
-- ``CHIPFLOW_API_ENDPOINT``: Custom API endpoint (defaults to production)
+- ``CHIPFLOW_ROOT``: Root directory of your project, which must contain `chipflow.toml`
+- ``CHIPFLOW_API_KEY``: API key secret for ChipFlow services
+- ``CHIPFLOW_API_ENDPOINT``: Custom API endpoint (defaults to production - https://build.chipflow.org)
 - ``CHIPFLOW_DEBUG``: Enable debug logging (set to "1")
-- ``CHIPFLOW_CONFIG``: Custom path to chipflow.toml file
 
 Using Custom Steps
 ------------------
@@ -221,20 +219,20 @@ To implement a custom step implementation:
    .. code-block:: python
 
       from chipflow_lib.steps.silicon import SiliconStep
-      
+
       class CustomSiliconStep(SiliconStep):
           def prepare(self):
               # Custom preparation logic
               result = super().prepare()
               # Additional processing
               return result
-              
+
           def submit(self, rtlil_path, *, dry_run=False):
               # Custom submission logic
               if dry_run:
                   # Custom dry run behavior
                   return
-                  
+
               # Custom submission implementation
               # ...
 
@@ -258,13 +256,13 @@ For complex pin requirements:
    # Differential pair
    lvds_in_p = { type = "i", loc = "N4", diff_pair = "positive" }
    lvds_in_n = { type = "i", loc = "N5", diff_pair = "negative" }
-   
+
    # Multiple bits of a bus
    data[0] = { type = "io", loc = "S1" }
    data[1] = { type = "io", loc = "S2" }
    data[2] = { type = "io", loc = "S3" }
    data[3] = { type = "io", loc = "S4" }
-   
+
    # Special I/O modes
    spi_clk = { type = "o", loc = "E1", drive = "8mA", slew = "fast" }
    i2c_sda = { type = "io", loc = "W1", pull = "up", schmitt = true }
@@ -278,14 +276,4 @@ ChipFlow integrates with Git for version tracking:
 2. ChipFlow warns if submitting from a dirty Git tree
 3. Version information is embedded in the manufacturing metadata
 
-For CI/CD integration, set the following environment variables:
-
-.. code-block:: bash
-
-   # CI/CD environment variables
-   export CHIPFLOW_CI=1
-   export CHIPFLOW_NONINTERACTIVE=1
-   
-   # Authentication
-   export CHIPFLOW_API_KEY_ID=your_ci_key_id
-   export CHIPFLOW_API_KEY_SECRET=your_ci_key_secret
+For CI/CD integration, call the `chipflow` command as usual, and make sure to set your `CHIPFLOW_API_KEY` using your CI providers' secret handling.

docs/workflows.rst renamed to docs/unfinished/workflows.rst

@@ -24,10 +24,10 @@ The simulation workflow allows you to test your design in a virtual environment
 .. code-block:: bash
 
    # Prepare the simulation environment
-   python -m chipflow_lib.cli sim prepare
+   pdm chipflow sim prepare
 
    # Run the simulation tests
-   python -m chipflow_lib.cli sim run
+   pdm chipflow sim run
 
 **Key Configuration:**
 
@@ -98,10 +98,10 @@ The board workflow prepares your design for FPGA deployment, which is useful for
 .. code-block:: bash
 
    # Prepare the design for FPGA deployment
-   python -m chipflow_lib.cli board prepare
+   pdm chipflow board prepare
 
    # Deploy to FPGA
-   python -m chipflow_lib.cli board deploy
+   pdm chipflow board deploy
 
 **Key Configuration:**
 
@@ -128,16 +128,16 @@ The silicon workflow is the path to producing actual ASICs through ChipFlow's ma
 .. code-block:: bash
 
    # Prepare design for manufacturing
-   python -m chipflow_lib.cli silicon prepare
+   pdm chipflow silicon prepare
 
    # Validate the design against manufacturing rules
-   python -m chipflow_lib.cli silicon validate
+   pdm chipflow silicon validate
 
    # Submit the design for manufacturing
-   python -m chipflow_lib.cli silicon submit
+   pdm chipflow silicon submit
 
    # Check the status of a submitted design
-   python -m chipflow_lib.cli silicon status
+   pdm chipflow silicon status
 
 **Key Configuration:**
 
@@ -186,16 +186,15 @@ To submit a design, you'll need to set up authentication:
 
    .. code-block:: bash
 
-      CHIPFLOW_API_KEY_ID=your_key_id
-      CHIPFLOW_API_KEY_SECRET=your_key_secret
+      CHIPFLOW_API_KEY=your_key_secret
 
 2. Alternatively, set these as environment variables before submission:
 
    .. code-block:: bash
 
       export CHIPFLOW_API_KEY_ID=your_key_id
       export CHIPFLOW_API_KEY_SECRET=your_key_secret
-      python -m chipflow_lib.cli silicon submit
+      pdm chipflow silicon submit
 
 Customizing Workflows
 ---------------------