wip -nearly working

Author: robtaylor

chipflow_lib/__init__.py

@@ -44,7 +44,7 @@ def _ensure_chipflow_root():
 
     if os.environ["CHIPFLOW_ROOT"] not in sys.path:
         sys.path.append(os.environ["CHIPFLOW_ROOT"])
-    _ensure_chipflow_root.root = os.environ["CHIPFLOW_ROOT"]
+    _ensure_chipflow_root.root = Path(os.environ["CHIPFLOW_ROOT"]).absolute()
     return _ensure_chipflow_root.root
 
 

chipflow_lib/platforms/silicon.py

@@ -139,6 +139,7 @@ def pins(self):
     def invert(self):
         return self._invert
 
+
     def __len__(self):
         if self._direction is io.Direction.Input:
             return len(self._i)

chipflow_lib/platforms/sim.py

@@ -110,20 +110,20 @@ def instantiate_ports(self, m: Module):
                 for name, port in v.items():
                     self._ports[port.port_name] = SiliconPlatformPort(component, name, port)
 
-        for clock, name in self._config["chipflow"]["clocks"].items():
-            if name not in pinlock.package.clocks:
-                raise ChipFlowError("Unable to find clock {name} in pinlock")
+        #for clock, name in self._config["chipflow"]["clocks"].items():
+        #    if name not in pinlock.package.clocks:
+        #        raise ChipFlowError("Unable to find clock {name} in pinlock")
 
-            port_data = pinlock.package.clocks[name]
-            port = SiliconPlatformPort(component, name, port_data, invert=True)
-            self._ports[name] = port
+        #    port_data = pinlock.package.clocks[name]
+        #    port = io.SimulationPort(component, name, port_data, invert=True)
+        #    self._ports[name] = port
 
-            if clock == 'default':
-                clock = 'sync'
-            setattr(m.domains, clock, ClockDomain(name=clock))
-            clk_buffer = io.Buffer("i", port)
-            setattr(m.submodules, "clk_buffer_" + clock, clk_buffer)
-            m.d.comb += ClockSignal().eq(clk_buffer.i)
+        #    if clock == 'default':
+        #        clock = 'sync'
+        #    setattr(m.domains, clock, ClockDomain(name=clock))
+        #    clk_buffer = io.Buffer("i", port)
+        #    setattr(m.submodules, "clk_buffer_" + clock, clk_buffer)
+        #    m.d.comb += ClockSignal().eq(clk_buffer.i)
 
         for reset, name in self._config["chipflow"]["resets"].items():
             port_data = pinlock.package.resets[name]
@@ -142,14 +142,15 @@ def instantiate_ports(self, m: Module):
     "OUTPUT_DIR": "./build/sim",
     "ZIG_CXX": f"{sys.executable} -m ziglang c++",
     "CXXFLAGS": "-O3 -g -std=c++17 -Wno-array-bounds -Wno-shift-count-overflow -fbracket-depth=1024",
+    "DEFINES": "-DPROJECT_ROOT=\\\"{PROJECT_ROOT}\\\" -DBUILD_DIR=\\\"{BUILD_DIR}\\\"",
     "INCLUDES": "-I {OUTPUT_DIR} -I {COMMON_DIR} -I {COMMON_DIR}/vendor -I {RUNTIME_DIR}",
 }
 DOIT_CONFIG = {'action_string_formatting': 'both'}
 
 BUILD_SIM = {
         "name": "build_sim",
         "actions": [
-            "{ZIG_CXX} {CXXFLAGS} {INCLUDES} -o {OUTPUT_DIR}/sim_soc{EXE} "
+            "{ZIG_CXX} {CXXFLAGS} {INCLUDES} {DEFINES} -o {OUTPUT_DIR}/sim_soc{EXE} "
             "{OUTPUT_DIR}/sim_soc.cc {SOURCE_DIR}/main.cc {COMMON_DIR}/models.cc"
             ],
         "targets": [

chipflow_lib/platforms/utils.py

@@ -6,7 +6,7 @@
 import pydantic
 
 from collections import OrderedDict, deque
-from collections.abc import MutableMapping
+from collections.abc import MutableMapping, Iterable
 from pprint import pformat
 from typing import Set, List, Dict, Optional, Union, Literal
 
@@ -73,11 +73,16 @@ class IOSignature(wiring.Signature):
 
     :param direction: Input, Output or Bidir
     :param width: width of port, default is 1
-    :param all_have_oe: controls whether each output wire is associated with an individual Output Enable bit or a single OE bit will be used for entire port, the default value is False, indicating that a single OE bit controls the entire port.
+    :param invert: Polarity inversion. If the value is a simple :class:`bool`, it specifies inversion for
+         the entire port. If the value is an iterable of :class:`bool`, the iterable must have the
+         same length as the width of :py:`io`, and the inversion is specified for individual wires.
+    :param all_have_oe: controls whether each output wire is associated with an individual Output Enable bit
+         or a single OE bit will be used for entire port, the default value is False, indicating that a
+         single OE bit controls the entire port.
     :param init: a  :ref:`const-castable object <lang-constcasting>` for the initial values of the port
     """
 
-    def __init__(self, direction: io.Direction, width: int = 1, all_have_oe: bool = False, init = None):
+    def __init__(self, direction: io.Direction, width: int = 1, invert: Union[bool,Iterable[bool]] = False, all_have_oe: bool = False, init = None):
         self._direction = direction
         self._width = width
         self._init = init
@@ -98,6 +103,17 @@ def __init__(self, direction: io.Direction, width: int = 1, all_have_oe: bool =
                 "all_have_oe": all_have_oe,
                 "init": init,
                 }
+        match invert:
+            case bool():
+                self._invert = (invert,) * self._width
+            case Iterable():
+              self._invert = tuple(invert)
+              if len(self._invert) != self._width:
+                  raise ValueError(f"Length of 'invert' ({len(self._invert)}) doesn't match "
+                                   f"length of 'io' ({len(self._io)})")
+            case _:
+                raise TypeError(f"'invert' must be a bool or iterable of bool, not {invert!r}")
+
 
         super().__init__(sig)
 
@@ -110,6 +126,10 @@ def width(self) -> int:
         "The width of the IO port, in wires"
         return self._width
 
+    def invert(self) -> int:
+        "A tuple as wide as the IO port, with a bool for the polarity inversion for each wire"
+        return self._invert
+
     def options(self) -> dict:
         """
         Options set on the io port at construction
@@ -356,6 +376,7 @@ class Port(pydantic.BaseModel):
     pins: List[str]
     port_name: str
     direction: Optional[str] = None
+    invert: Union[bool, Iterable[bool]] = False
     options: Optional[dict] = None
 
     @property

chipflow_lib/steps/sim.py

@@ -12,12 +12,13 @@
 
 from amaranth import *
 from amaranth.lib import wiring, io
+from amaranth.lib.cdc import FFSynchronizer
 from amaranth.back import rtlil
+from amaranth.hdl._ir import PortDirection
 
-from .. import ChipFlowError
+from .. import ChipFlowError, _ensure_chipflow_root
 from . import StepBase
 from ..platforms import SiliconPlatform, top_interfaces, load_pinlock
-from ..platforms.silicon import SiliconPlatformPort, FFSynchronizer
 from ..platforms.utils import IOSignature, load_pinlock, Port
 from ..platforms.sim import VARIABLES, TASKS, DOIT_CONFIG
 
@@ -35,10 +36,11 @@ def common():
 
 @contextmanager
 def source():
-    sourcedir = importlib.resources.files("mcu_soc")
-    sim_src = sourcedir.joinpath('design','sim')
-    with importlib.resources.as_file(sim_src) as f:
-        yield f
+    root = _ensure_chipflow_root()
+    sourcedir = Path(root) / 'design' / 'sim'
+    #sim_src = sourcedir.joinpath('design','sim')
+    #with importlib.resources.as_file(sim_src) as f:
+    yield sourcedir
 
 @contextmanager
 def runtime():
@@ -92,7 +94,16 @@ def add_file(self, filename, content):
     def build(self, e):
         Path(self.build_dir).mkdir(parents=True, exist_ok=True)
 
-        output = rtlil.convert(e, name="sim_top", ports=self._ports, platform=self)
+        ports = []
+        for port_name, port in self._ports.items():
+            if port.direction in (io.Direction.Input, io.Direction.Bidir):
+                ports.append((f"io${port_name}$i", port.i, PortDirection.Input))
+            if port.direction in (io.Direction.Output, io.Direction.Bidir):
+                ports.append((f"io${port_name}$o", port.o, PortDirection.Output))
+            if port.direction is io.Direction.Bidir:
+                ports.append((f"io${port_name}$oe", port.oe, PortDirection.Output))
+
+        output = rtlil.convert(e, name="sim_top", ports=ports, platform=self)
 
         top_rtlil = Path(self.build_dir) / "sim_soc.il"
         with open(top_rtlil, "w") as rtlil_file:
@@ -120,14 +131,14 @@ def instantiate_ports(self, m: Module):
         for component, iface in pinlock.port_map.items():
             for k, v in iface.items():
                 for name, port in v.items():
-                    self._ports[port.port_name] = SiliconPlatformPort(component, name, port)
+                    self._ports[port.port_name] = io.SimulationPort(port.direction, port.width, invert=port.invert, name=f"{component}-{name}")
 
         for clock, name in self._config["chipflow"]["clocks"].items():
             if name not in pinlock.package.clocks:
                 raise ChipFlowError("Unable to find clock {name} in pinlock")
 
             port_data = pinlock.package.clocks[name]
-            port = SiliconPlatformPort(component, name, port_data, invert=True)
+            port = io.SimulationPort(io.Direction.Input, port_data.width, invert=True, name=f"clock-{name}")
             self._ports[name] = port
 
             if clock == 'default':
@@ -139,7 +150,7 @@ def instantiate_ports(self, m: Module):
 
         for reset, name in self._config["chipflow"]["resets"].items():
             port_data = pinlock.package.resets[name]
-            port = SiliconPlatformPort(component, name, port_data)
+            port = io.SimulationPort(io.Direction.Input, port_data.width, invert=port.invert, name=f"clock-{name}", )
             self._ports[name] = port
             rst_buffer = io.Buffer("i", port)
             setattr(m.submodules, reset, rst_buffer)
@@ -177,15 +188,23 @@ def build(self):
                     iface = getattr(top[component], iface_name)
                     wire = (iface if isinstance(iface.signature, IOSignature)
                             else getattr(iface, name))
-                    self._platform._ports[port.port_name].wire(m, wire)
+                    port = self._platform._ports[port.port_name]
+                    if hasattr(wire, 'i'):
+                        m.d.comb += wire.i.eq(port.i)
+                    for d in ['o', 'oe']:
+                        if hasattr(wire, d):
+                            m.d.comb += getattr(port, d).eq(getattr(wire, d))
 
 
+        #FIXME: common source for build dir
         self._platform.build(m)
         with common() as common_dir, source() as source_dir, runtime() as runtime_dir:
             context = {
                 "COMMON_DIR": common_dir,
                 "SOURCE_DIR": source_dir,
                 "RUNTIME_DIR": runtime_dir,
+                "PROJECT_ROOT": _ensure_chipflow_root(),
+                "BUILD_DIR": _ensure_chipflow_root() / 'build',
                 "EXE": EXE,
                 }
             for k,v in VARIABLES.items():