Fix import scoping and naming for PackageDefs

Author: robtaylor

chipflow_lib/pin_lock.py

@@ -7,8 +7,15 @@
 from typing import Any, List, Dict, Tuple
 
 from chipflow_lib import _parse_config, ChipFlowError
-from chipflow_lib.platforms import PACKAGE_DEFINITIONS, PIN_ANNOTATION_SCHEMA, top_interfaces
-from chipflow_lib.platforms.utils import LockFile, Package, PortMap, Port
+from chipflow_lib.platforms import (
+        PACKAGE_DEFINITIONS,
+        PIN_ANNOTATION_SCHEMA,
+        top_interfaces,
+        LockFile,
+        Package,
+        PortMap,
+        Port
+)
 from chipflow_lib.config_models import Config
 
 # logging.basicConfig(stream=sys.stdout, level=logging.DEBUG)

chipflow_lib/platforms/utils.py

@@ -19,7 +19,8 @@
 
 __all__ = ['PIN_ANNOTATION_SCHEMA', 'PinSignature',
            'OutputPinSignature', 'InputPinSignature', 'BidirPinSignature',
-           'load_pinlock', "PACKAGE_DEFINITIONS", 'top_interfaces']
+           'load_pinlock', "PACKAGE_DEFINITIONS", 'top_interfaces', 'LockFile',
+           'Package', 'PortMap', 'Port']
 
 
 logger = logging.getLogger(__name__)
@@ -246,7 +247,7 @@ class _BareDiePackageDef(_BasePackageDef):
     """
 
     # Used by pydantic to differentate when deserialising
-    type: Literal["_QuadPackageDef"] = "_QuadPackageDef"
+    type: Literal["_BarePackageDef"] = "_BarePackageDef"
 
     width: int
     height: int
@@ -278,7 +279,7 @@ class _QuadPackageDef(_BasePackageDef):
     """
 
     # Used by pydantic to differentate when deserialising
-    type: Literal["_PGAPackageDef"] = "_PGAPackageDef"
+    type: Literal["_QuadPackageDef"] = "_QuadPackageDef"
 
     width:int
     height: int
@@ -311,7 +312,7 @@ def sortpins(self, pins: Union[List[str], Set[str]]) -> List[str]:
     "cf20": _BareDiePackageDef(name="cf20", width=7, height=3)
 }
 
-PackageDef = Union[_QuadPackageDef, _BasePackageDef]
+PackageDef = Union[_QuadPackageDef, _BareDiePackageDef]
 
 
 class Port(pydantic.BaseModel):