Add openframe package support

Author: robtaylor

chipflow_lib/_appresponse.py

@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: BSD-2-Clause
+
+from dataclasses import dataclass
+
+from pydantic import BaseModel, PlainSerializer, model_serializer
+
+@dataclass
+class OmitIfNone:
+    pass
+
+class AppResponseModel(BaseModel):
+    @model_serializer
+    def _serialize(self):
+        skip_if_none = set()
+        serialize_aliases = dict()
+
+        # Gather fields that should omit if None
+        for name, field_info in self.model_fields.items():
+            if any(
+                isinstance(metadata, OmitIfNone) for metadata in field_info.metadata
+            ):
+                skip_if_none.add(name)
+            elif field_info.serialization_alias:
+                serialize_aliases[name] = field_info.serialization_alias
+
+        serialized = dict()
+
+        for name, value in self:
+            # Skip serializing None if it was marked with "OmitIfNone"
+            if value is None and name in skip_if_none:
+                continue
+            serialize_key = serialize_aliases.get(name, name)
+
+            # Run Annotated PlainSerializer
+            for metadata in self.model_fields[name].metadata:
+                if isinstance(metadata, PlainSerializer):
+                    value = metadata.func(value)  # type: ignore
+
+            serialized[serialize_key] = value
+
+        return serialized

chipflow_lib/cli.py

@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: BSD-2-Clause
+
 import argparse
 import inspect
 import sys

chipflow_lib/config_models.py

@@ -1,63 +1,23 @@
 # SPDX-License-Identifier: BSD-2-Clause
-import re
-from typing import Dict, Optional, Literal, Any, List
+from typing import Dict, Optional, Any, List
 
-from pydantic import BaseModel, model_validator, ValidationInfo, field_validator
+from pydantic import BaseModel
 
-from .platforms.utils import Process
+from .platforms._internal import PACKAGE_DEFINITIONS, Process, Voltage
 
-class PadConfig(BaseModel):
-    """Configuration for a pad in chipflow.toml."""
-    type: Literal["io", "i", "o", "oe", "clock", "reset", "power", "ground"]
-    loc: str
 
-    @model_validator(mode="after")
-    def validate_loc_format(self):
-        """Validate that the location is in the correct format."""
-        if not re.match(r"^[NSWE]?[0-9]+$", self.loc):
-            raise ValueError(f"Invalid location format: {self.loc}, expected format: [NSWE]?[0-9]+")
-        return self
+def known_package(package: str):
+    if package not in PACKAGE_DEFINITIONS.keys():
+        raise ValueError(f"{package} is not a valid package type. Valid package types are {PACKAGE_DEFINITIONS.keys()}")
 
-    @classmethod
-    def validate_pad_dict(cls, v: dict, info: ValidationInfo):
-        """Custom validation for pad dicts from TOML that may not have all fields."""
-        if isinstance(v, dict):
-            # Handle legacy format - if 'type' is missing but should be inferred from context
-            if 'loc' in v and 'type' not in v:
-                if info.field_name == 'power':
-                    v['type'] = 'power'
-
-            # Map legacy 'clk' type to 'clock' to match our enum
-            if 'type' in v and v['type'] == 'clk':
-                v['type'] = 'clock'
-
-            return v
-        return v
-
-
-Voltage = float
 
 class SiliconConfig(BaseModel):
     """Configuration for silicon in chipflow.toml."""
     process: 'Process'
-    package: Literal["caravel", "cf20", "pga144"]
+    package: str
     power: Dict[str, Voltage] = {}
     debug: Optional[Dict[str, bool]] = None
     # This is still kept around to allow forcing pad locations.
-    pads: Optional[Dict[str, PadConfig]] = {}
-
-    @field_validator('pads', 'power', mode='before')
-    @classmethod
-    def validate_pad_dicts(cls, v, info: ValidationInfo):
-        """Pre-process pad dictionaries to handle legacy format."""
-        if isinstance(v, dict):
-            result = {}
-            for key, pad_dict in v.items():
-                # Apply the pad validator with context about which field we're in
-                validated_pad = PadConfig.validate_pad_dict(pad_dict, info)
-                result[key] = validated_pad
-            return result
-        return v
 
 
 class ChipFlowConfig(BaseModel):

chipflow_lib/pin_lock.py

@@ -6,7 +6,7 @@
 from pprint import pformat
 
 from . import _parse_config, _ensure_chipflow_root, ChipFlowError
-from .platforms import top_components, LockFile, PACKAGE_DEFINITIONS
+from .platforms._internal import top_components, LockFile, PACKAGE_DEFINITIONS
 
 # logging.basicConfig(stream=sys.stdout, level=logging.DEBUG)
 logger = logging.getLogger(__name__)

chipflow_lib/platforms/__init__.py

@@ -6,15 +6,16 @@
 
 """
 
-from .silicon import *
-from .sim import *
-from .utils import *
+from .silicon import SiliconPlatformPort, SiliconPlatform
+from .sim import SimPlatform
+from .utils import (
+        IO_ANNOTATION_SCHEMA, IOSignature, IOModel,
+        OutputIOSignature, InputIOSignature, BidirIOSignature,
+        )
+from ._packages import PACKAGE_DEFINITIONS
 
 __all__ = ['IO_ANNOTATION_SCHEMA', 'IOSignature', 'IOModel',
            'OutputIOSignature', 'InputIOSignature', 'BidirIOSignature',
-           'load_pinlock', "PACKAGE_DEFINITIONS", 'top_components', 'LockFile',
-           'Package', 'PortMap', 'Port', 'Process',
-           'GAPackageDef', 'QuadPackageDef', 'BareDiePackageDef', 'BasePackageDef',
-           'BringupPins', 'JTAGPins', 'PowerPins',
            'SiliconPlatformPort', 'SiliconPlatform',
-           'SimPlatform']
+           'SimPlatform',
+           'PACKAGE_DEFINITIONS']

chipflow_lib/platforms/_internal.py

@@ -0,0 +1,12 @@
+from .silicon import *
+from .sim import *
+from .utils import *
+from ._packages import *
+__all__ = ['IO_ANNOTATION_SCHEMA', 'IOSignature', 'IOModel',
+           'OutputIOSignature', 'InputIOSignature', 'BidirIOSignature',
+           'load_pinlock', "PACKAGE_DEFINITIONS", 'top_components', 'LockFile',
+           'Package', 'PortMap', 'PortDesc', 'Process',
+           'GAPackageDef', 'QuadPackageDef', 'BareDiePackageDef', 'BasePackageDef',
+           'BringupPins', 'JTAGPins', 'PowerPins',
+           'SiliconPlatformPort', 'SiliconPlatform',
+           'SimPlatform']

chipflow_lib/platforms/_openframe.py

@@ -0,0 +1,125 @@
+from typing import List, NamedTuple, Optional, Literal
+
+from .utils import Voltage, PowerPins, LinearAllocPackageDef, BringupPins
+
+class OFPin(NamedTuple):
+    pin: int
+    kind: str
+    idx: int = 0
+    voltage: Optional[Voltage] = None
+    name: Optional[str] = None
+
+OF_GPIO = [
+    OFPin(31, "gpio", 0),  # gpio[0]
+    OFPin(32, "gpio", 1),  # gpio[1]
+    OFPin(33, "gpio", 2),  # gpio[2]
+    OFPin(34, "gpio", 3),  # gpio[3]
+    OFPin(35, "gpio", 4),  # gpio[4]
+    OFPin(36, "gpio", 5),  # gpio[5]
+    OFPin(37, "gpio", 6),  # gpio[6]
+    OFPin(41, "gpio", 7),  # gpio[7]
+    OFPin(42, "gpio", 8),  # gpio[8]
+    OFPin(43, "gpio", 9),  # gpio[9]
+    OFPin(44, "gpio", 10),  # gpio[10]
+    OFPin(45, "gpio", 11),  # gpio[11]
+    OFPin(46, "gpio", 12),  # gpio[12]
+    OFPin(48, "gpio", 13),  # gpio[13]
+    OFPin(50, "gpio", 14),  # gpio[14]
+    OFPin(51, "gpio", 15),  # gpio[15]
+    OFPin(53, "gpio", 16),  # gpio[16]
+    OFPin(54, "gpio", 17),  # gpio[17]
+    OFPin(55, "gpio", 18),  # gpio[18]
+    OFPin(57, "gpio", 19),  # gpio[19]
+    OFPin(58, "gpio", 20),  # gpio[20]
+    OFPin(59, "gpio", 21),  # gpio[21]
+    OFPin(60, "gpio", 22),  # gpio[22]
+    OFPin(61, "gpio", 23),  # gpio[23]
+    OFPin(62, "gpio", 24),  # gpio[24]
+    OFPin(2, "gpio", 25),  # gpio[25]
+    OFPin(3, "gpio", 26),  # gpio[26]
+    OFPin(4, "gpio", 27),  # gpio[27]
+    OFPin(5, "gpio", 28),  # gpio[28]
+    OFPin(6, "gpio", 29),  # gpio[29]
+    OFPin(7, "gpio", 30),  # gpio[30]
+    OFPin(8, "gpio", 31),  # gpio[31]
+    OFPin(11, "gpio", 32),  # gpio[32]
+    OFPin(12, "gpio", 33),  # gpio[33]
+    OFPin(13, "gpio", 34),  # gpio[34]
+    OFPin(14, "gpio", 35),  # gpio[35]
+    OFPin(15, "gpio", 36),  # gpio[36]
+    OFPin(16, "gpio", 37),  # gpio[37]
+    # OFPin(22, "gpio", 38)   # gpio[38] is assigned as clock
+    # OFPin(24, "gpio", 39)   # gpio[39] is assigned as heartbeat
+    # OFPin(25, "gpio", 40),  # gpio[40] is assign as reset
+    OFPin(26, "gpio", 41),  # gpio[41]
+    OFPin(27, "gpio", 42),  # gpio[42]
+    OFPin(28, "gpio", 43),  # gpio[43]
+]
+
+OF_CLOCK_PIN = OFPin(22, "gpio", 38)
+OF_HEARTBEAT_PIN = OFPin(24, "gpio", 39)
+OF_RESET_PIN = OFPin(25, "gpio", 40)
+
+OF_CORE_POWER = [
+    (OFPin(18,"vcc", voltage=1.8, name="d"),     # Power, Digital power supply
+     OFPin(23,"vss", name="d")),                 # Digital power ground
+]
+
+OF_OTHER_POWER= [
+    (OFPin(30,"vdd", voltage=3.3, name="a"),     # Power, Analog power supply
+     OFPin(20,"vss", name="a")),                 # Analog power ground
+
+    (OFPin(49,"vcc", voltage=1.8, name="d1"),    # Power, Digital power supply
+     OFPin(39,"vss", name="d1")),                # Digital power ground
+
+    (OFPin(17,"vdd", voltage=3.3, name="io"),    # Power, ESD and padframe power supply
+     OFPin(29,"vss", name="io")),                # ESD and padframe ground
+
+    (OFPin(64,"vdd", voltage=3.3, name="io"),    # Power, ESD and padframe power supply
+     OFPin(56,"vss", name="io")),                # ESD and padframe ground
+
+    (OFPin(63,"vcc", voltage=1.8, name="d2"),    # Power, Digital power supply
+     OFPin(10,"vss", name="d2")),                # Digital power ground
+
+    (OFPin(40,"vdd", voltage=3.3, name="a1"),    # Power,  Analog power supply
+     OFPin(38,"vss", name="a1")),                # Analog power ground
+
+    (OFPin(47,"vdd", voltage=3.3, name="a1"),    # Power,  Analog power supply
+     OFPin(52,"vss", name="a1")),                # Analog power ground
+
+    (OFPin(9,"vdd", voltage=3.3, name="a2"),     # Power,  Analog power supply
+     OFPin(1,"vss", name="a2")),                 # Analog power ground
+]
+
+OF_OTHER = [
+    OFPin(19, "NC")  # Not connected
+]
+
+class OpenframePackageDef(LinearAllocPackageDef):
+
+    name: str = "openframe"
+    package_type: Literal["OpenframePackageDef"] = "OpenframePackageDef"
+    def model_post_init(self, __context):
+        self._ordered_pins = OF_GPIO
+
+        super().model_post_init(__context)
+
+
+    @property
+    def _core_power(self) -> List[PowerPins]:
+        pps = []
+
+        for power, ground in OF_CORE_POWER:
+            pp = PowerPins(power=power, ground=ground, voltage=power.voltage)
+            pps.append(pp)
+
+        return pps
+
+    @property
+    def bringup_pins(self) -> BringupPins:
+        return BringupPins(
+            core_power=self._core_power,
+            core_clock=OF_CLOCK_PIN,
+            core_reset=OF_RESET_PIN,
+            core_heartbeat=OF_HEARTBEAT_PIN,
+        )

chipflow_lib/platforms/_packages.py

@@ -0,0 +1,11 @@
+from .utils import QuadPackageDef, BareDiePackageDef, GAPackageDef, Package
+from ._openframe import OpenframePackageDef
+
+# Add any new package types to both PACKAGE_DEFINITIONS and the PackageDef union
+PACKAGE_DEFINITIONS = {
+    "pga144": QuadPackageDef(name="pga144", width=36, height=36),
+    "cf20": BareDiePackageDef(name="cf20", width=7, height=3),
+    "openframe": OpenframePackageDef()
+}
+
+Package.model_rebuild()