Updated to have single process in configs for now.

Author: lanserge

chipflow_lib/__init__.py

@@ -74,17 +74,14 @@ def _ensure_chipflow_root():
                 "silicon": {
                     "type": "object",
                     "required": [
-                        "processes",
+                        "process",
                         "package",
                     ],
                     "additionalProperties": False,
                     "properties": {
-                        "processes": {
-                            "type": "array",
-                            "items": {
-                                "type": "string",
-                                "enum": ["sky130", "gf180", "customer1", "gf130bcd", "ihp_sg13g2"]
-                            }
+                        "process": {
+                            "type": "string",
+                            "enum": ["sky130", "gf180", "customer1", "gf130bcd", "ihp_sg13g2"]
                         },
                         "package": {
                             "enum": ["caravel", "cf20", "pga144"]

chipflow_lib/pin_lock.py

@@ -86,7 +86,7 @@ def lock_pins() -> None:
         oldlock = LockFile.model_validate_json(json_string)
 
     print(f"Locking pins: {'using pins.lock' if lockfile.exists() else ''}")
-    processes = config["chipflow"]["silicon"]["process"]
+    process_name = config["chipflow"]["silicon"]["process"]
     package_name = config["chipflow"]["silicon"]["package"]
 
     if package_name not in PACKAGE_DEFINITIONS:
@@ -146,7 +146,7 @@ def lock_pins() -> None:
                 _map, _ = allocate_pins(k, v, pins)
                 port_map.add_ports(component, k, _map)
 
-    newlock = LockFile(processes=processes,
+    newlock = LockFile(process=process_name,
                        package=package,
                        port_map=port_map,
                        metadata=interfaces)

chipflow_lib/platforms/utils.py

@@ -416,7 +416,7 @@ class LockFile(pydantic.BaseModel):
         port_map: Mapping of components to interfaces to port
         metadata: Amaranth metadata, for reference
     """
-    processes: List[Process]
+    process: Process
     package: Package
     port_map: PortMap
     metadata: dict

chipflow_lib/steps/silicon.py

@@ -152,7 +152,7 @@ def submit(self, rtlil_path, *, dry_run=False):
         config = {
             "dependency_versions": dep_versions,
             "silicon": {
-                "process": self.silicon_config["processes"][0],
+                "process": self.silicon_config["process"],
                 "pad_ring": self.silicon_config["package"],
                 "pads": pads,
                 "power": self.silicon_config.get("power", {})