Assign io power pins

Author: robtaylor

chipflow_lib/platforms/_packages.py

@@ -1,10 +1,11 @@
-from ._utils import QuadPackageDef, BareDiePackageDef, Package
+from ._utils import QuadPackageDef, BareDiePackageDef, GAPackageDef, Package
 from ._openframe import OpenframePackageDef
 
 # Add any new package types to both PACKAGE_DEFINITIONS and the PackageDef union
 PACKAGE_DEFINITIONS = {
     "pga144": QuadPackageDef(name="pga144", width=36, height=36),
     "cf20": BareDiePackageDef(name="cf20", width=7, height=3),
+    "bga144": GAPackageDef(name="bga144", width=36, height=36),
     "openframe": OpenframePackageDef()
 }
 

chipflow_lib/platforms/_utils.py

@@ -664,8 +664,8 @@ def _allocate_bringup(self, config: 'Config') -> Component:
             vss = "vss"
             vdd = "vdd"
             if pp.name:
-                vss = f"vss{pp.name}"
-                vdd = f"vdd{pp.name}"
+                vss = f"{pp.name}vss"
+                vdd = f"{pp.name}vdd"
             powerpins[vss].append(pp.power)
             powerpins[vdd].append(pp.ground)
 
@@ -769,12 +769,14 @@ def model_post_init(self, __context):
 
     @property
     def bringup_pins(self) -> BringupPins:
-        core_power = PowerPins(
-            (_Side.N, 1),
-            (_Side.N, 2)
-        )
+        #TODO, this makes no sense for anything that isn't tiny..
+        core_power = [
+                PowerPins((_Side.N, 1), (_Side.N, 2)),
+                PowerPins((_Side.W, 1), (_Side.W, 2), name='d')
+                ]
+
         return BringupPins(
-            core_power=[core_power],
+            core_power=core_power,
             core_clock=(_Side.N, 3),
             core_reset=(_Side.N, 3),
             core_heartbeat=(_Side.E, 1),
@@ -849,27 +851,34 @@ def _power(self) -> List[PowerPins]:
         Power pins are always a matched pair in the middle of a side, with the number
         varying with the size of the package.
         We don't move power pins from these locations to allow for easier bring up test.
+        returns two lists, core power pins and io power pins
         """
-        pins = []
+        pins: List[PowerPins] = []
+        # heuristic for sensible number of power pins for a given size
         n = (self.width + self.height)//12
         # Left
         p = self.height//2 + self.height//2
-        pins.append(PowerPins(p, p +1))
+        assert p > 3
+        pins.append(PowerPins(p-2, p-1))
+        pins.append(PowerPins(p, p+1, name='d'))
         # Bottom
         start = self.height
         if n > 2:
-            p = start + self.width//2 + self.width//2
-            pins.append(PowerPins(p, p+1))
+            p = start + self.width//2
+            pins.append(PowerPins(p-2, p-1))
+            pins.append(PowerPins(p, p+1, name='d'))
         # Right
         start = start + self.width
         if n > 1:
-            p = start + self.height//2 + self.height//2
-            pins.append(PowerPins(p, p+1))
+            p = start + self.height//2
+            pins.append(PowerPins(p-2, p-1))
+            pins.append(PowerPins(p, p+1, name='d'))
         # Top
         start = start + self.height
         if n > 3:
-            p = start + self.width//2 + self.width//2
-            pins.append(PowerPins(p, p+1))
+            p = start + self.width//2
+            pins.append(PowerPins(p-2, p-1))
+            pins.append(PowerPins(p, p+1, name='d'))
         return pins
 
 
@@ -961,75 +970,77 @@ class GAPackageDef(BasePackageDef):
     width:int
     height: int
     layout_type: GALayout= GALayout.FULL
-    channel_width: Optional[int]
-    island_width: Optional[int]
-    missing_pins: Optional[Set[GAPin]]
-    additional_pins: Optional[Set[GAPin]]
-
-    def model_post_init(self, __context):
-        def int_to_alpha(i: int):
-            "Covert int to alpha representation, starting at 1"
-            valid_letters = "ABCDEFGHJKLMPRSTUVWXY"
-            out = ''
-            while i > 0:
-                char = i % len(valid_letters)
-                i = i // len(valid_letters)
-                out = valid_letters[char-1] + out
-            return out
-
+    channel_width: Optional[int] = None
+    island_width: Optional[int] = None
+    missing_pins: Optional[Set[GAPin]] = None
+    additional_pins: Optional[Set[GAPin]] = None
+
+    @staticmethod
+    def _int_to_alpha(i: int):
+        "Covert int to alpha representation, starting at 1"
+        valid_letters = "ABCDEFGHJKLMPRSTUVWXY"
+        out = ''
+        while i > 0:
+            char = i % len(valid_letters)
+            i = i // len(valid_letters)
+            out = valid_letters[char-1] + out
+        return out
+
+    def _get_all_pins(self) -> Tuple[Set[GAPin], Set[GAPin] | None]:
         def pins_for_range(h1: int, h2: int, w1: int, w2: int) -> Set[GAPin]:
-            pins = [GAPin(int_to_alpha(h),w) for h in range(h1, h2) for w in range(w1, w2)]
+            pins = [GAPin(self._int_to_alpha(h),w) for h in range(h1, h2) for w in range(w1, w2)]
             return set(pins)
 
-        def sort_by_quadrant(pins: Set[GAPin]) -> List[Pin]:
-            quadrants:List[Set[GAPin]] = [set(), set(), set(), set()]
-            midline_h = int_to_alpha(self.height // 2)
-            midline_w = self.width // 2
-            for pin in pins:
-                if pin.h < midline_h and pin.w < midline_w:
-                    quadrants[0].add(pin)
-                if pin.h >= midline_h and pin.w < midline_w:
-                    quadrants[1].add(pin)
-                if pin.h < midline_h and pin.w >= midline_w:
-                    quadrants[2].add(pin)
-                if pin.h >= midline_h and pin.w >= midline_w:
-                    quadrants[3].add(pin)
-            ret = []
-            for q in range(0,3):
-                ret.append(sorted(quadrants[q]))
-            return ret
 
-        self._ordered_pins: List[Pin] = []
         match self.layout_type:
             case GALayout.FULL:
                 pins = pins_for_range(1, self.height, 1, self.width)
-                pins -= self.bringup_pins.to_set()
-                self._ordered_pins = sort_by_quadrant(pins)
+                return (pins, None)
 
             case GALayout.PERIMETER:
                 assert self.channel_width is not None
                 pins = pins_for_range(1, self.height, 1, self.width) - \
                        pins_for_range(1 + self.channel_width, self.height-self.channel_width,  1 + self.channel_width, self.width - self.channel_width)
-                pins -= self.bringup_pins.to_set()
-                self._ordered_pins = sort_by_quadrant(pins)
+                return (pins, None)
 
             case GALayout.ISLAND:
                 assert self.channel_width is not None
                 assert self.island_width is not None
                 outer_pins = pins_for_range(1, self.height, 1, self.width) - \
                              pins_for_range(1 + self.channel_width, self.height-self.channel_width,  1 + self.channel_width, self.width - self.channel_width)
-                outer_pins -= self.bringup_pins.to_set()
                 inner_pins = pins_for_range(ceil(self.height/ 2 - self.island_width /2), floor(self.height/2 + self.island_width /2),
                                             ceil(self.width / 2 - self.island_width /2), floor(self.width /2 + self.island_width /2))
-                # TODO, allocate island as power
-                self._ordered_pins = sort_by_quadrant(outer_pins) + sorted(inner_pins)
+                return (outer_pins, inner_pins)
 
             case GALayout.CHANNEL:
                 assert self.channel_width is not None
                 pins = pins_for_range(1, self.channel_width + 1, 1, self.width) | \
                        pins_for_range(self.height - self.channel_width, self.height, 1, self.width)
-                pins -= self.bringup_pins.to_set()
-                self._ordered_pins = sort_by_quadrant(pins)
+                return (pins, None)
+
+    def model_post_init(self, __context):
+        def sort_by_quadrant(pins: Set[GAPin]) -> List[GAPin]:
+            quadrants:List[Set[GAPin]] = [set(), set(), set(), set()]
+            midline_h = self._int_to_alpha(self.height // 2)
+            midline_w = self.width // 2
+            for pin in pins:
+                if pin.h < midline_h and pin.w < midline_w:
+                    quadrants[0].add(pin)
+                if pin.h >= midline_h and pin.w < midline_w:
+                    quadrants[1].add(pin)
+                if pin.h < midline_h and pin.w >= midline_w:
+                    quadrants[2].add(pin)
+                if pin.h >= midline_h and pin.w >= midline_w:
+                    quadrants[3].add(pin)
+            ret = []
+            for q in range(0,3):
+                ret.append(sorted(quadrants[q]))
+            return ret
+
+        self._ordered_pins: List[GAPin] = []
+        pins, _ = self._get_all_pins()
+        pins -= self.bringup_pins.to_set()
+        self._ordered_pins = sort_by_quadrant(pins)
 
         return super().model_post_init(__context)
 
@@ -1061,8 +1072,31 @@ def bringup_pins(self) -> BringupPins:
 
     @property
     def _power(self) -> List[PowerPins]:
-        return [PowerPins(1,2)]
+        #TODO build an internal padring mapping
+        # for now, just distribute evenly
+        power_pins = []
 
+        pins, inner = self._get_all_pins()
+        #allocate all of inner to core pins, alternating
+        try:
+            if inner:
+                it = iter(sorted(inner))
+                for p in it:
+                    power_pins.append(PowerPins(p, next(it)))
+        except StopIteration:
+            pass
+        # distribute the rest evenly
+        try:
+            it = iter(sorted(pins))
+            for p in it:
+                for name in ('','d'):
+                    power_pins.append(PowerPins(p, next(it)))
+                for i in range(0,15):
+                    next(it)
+        except StopIteration:
+            pass
+
+        return power_pins
 
     @property
     def _jtag(self) -> JTAGPins:

chipflow_lib/platforms/silicon.py

@@ -14,7 +14,7 @@
 from amaranth import Module, Signal, ClockDomain, ClockSignal, ResetSignal, unsigned
 from amaranth.lib import wiring, io, data
 from amaranth.lib.cdc import FFSynchronizer
-from amaranth.lib.wiring import Component, In, PureInterface
+from amaranth.lib.wiring import Component, In
 from amaranth.back import rtlil  #type: ignore[reportAttributeAccessIssue]
 from amaranth.hdl import Fragment
 from amaranth.hdl._ir import PortDirection