diff --git a/chipflow_lib/steps/silicon.py b/chipflow_lib/steps/silicon.py
index e89306bb..357dcdbd 100644
--- a/chipflow_lib/steps/silicon.py
+++ b/chipflow_lib/steps/silicon.py
@@ -16,6 +16,7 @@
 from . import StepBase
 from .. import ChipFlowError
 from ..platforms import SiliconPlatform, top_interfaces, load_pinlock
+from ..platforms.utils import PinSignature
 
 
 logger = logging.getLogger(__name__)
@@ -46,10 +47,10 @@ def elaborate(self, platform: SiliconPlatform):
         for component, iface in platform.pinlock.port_map.items():
             for iface_name, member, in iface.items():
                 for name, port in member.items():
-                    platform.ports[port.port_name].wire(
-                            m,
-                            getattr(getattr(top[component], iface_name), name)
-                            )
+                    iface = getattr(top[component], iface_name)
+                    wire = (iface if isinstance(iface.signature, PinSignature)
+                            else getattr(iface, name))
+                    platform.ports[port.port_name].wire(m, wire)
         return m