From 684c285ef5dbc686c9b5de2b7c4745aeb5a4827e Mon Sep 17 00:00:00 2001 From: Serge Rabyking Date: Thu, 8 May 2025 18:15:58 +0100 Subject: [PATCH 1/2] Fixed instntiating direct pins in the ChipflowTop --- chipflow_lib/steps/silicon.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/chipflow_lib/steps/silicon.py b/chipflow_lib/steps/silicon.py index e89306bb..4b0b00a2 100644 --- a/chipflow_lib/steps/silicon.py +++ b/chipflow_lib/steps/silicon.py @@ -12,6 +12,7 @@ import dotenv from amaranth import * +from amaranth.lib.wiring import PureInterface from . import StepBase from .. import ChipFlowError @@ -46,10 +47,10 @@ def elaborate(self, platform: SiliconPlatform): for component, iface in platform.pinlock.port_map.items(): for iface_name, member, in iface.items(): for name, port in member.items(): - platform.ports[port.port_name].wire( - m, - getattr(getattr(top[component], iface_name), name) - ) + iface = getattr(top[component], iface_name) + wire = (iface if isinstance(iface, PureInterface) + else getattr(iface, name)) + platform.ports[port.port_name].wire(m, wire) return m From 13d1ae8b74144bd4439a1e4e8873f3dd478b6cb6 Mon Sep 17 00:00:00 2001 From: Serge Rabyking Date: Thu, 8 May 2025 18:44:42 +0100 Subject: [PATCH 2/2] Updated check for interfaces created from PinSignature --- chipflow_lib/steps/silicon.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chipflow_lib/steps/silicon.py b/chipflow_lib/steps/silicon.py index 4b0b00a2..357dcdbd 100644 --- a/chipflow_lib/steps/silicon.py +++ b/chipflow_lib/steps/silicon.py @@ -12,11 +12,11 @@ import dotenv from amaranth import * -from amaranth.lib.wiring import PureInterface from . import StepBase from .. import ChipFlowError from ..platforms import SiliconPlatform, top_interfaces, load_pinlock +from ..platforms.utils import PinSignature logger = logging.getLogger(__name__) @@ -48,7 +48,7 @@ def elaborate(self, platform: SiliconPlatform): for iface_name, member, in iface.items(): for name, port in member.items(): iface = getattr(top[component], iface_name) - wire = (iface if isinstance(iface, PureInterface) + wire = (iface if isinstance(iface.signature, PinSignature) else getattr(iface, name)) platform.ports[port.port_name].wire(m, wire) return m