diff --git a/chipflow_lib/cli.py b/chipflow_lib/cli.py
index a7c5a761..bf189416 100644
--- a/chipflow_lib/cli.py
+++ b/chipflow_lib/cli.py
@@ -65,7 +65,7 @@ def _ensure_chipflow_root():
                     "additionalProperties": False,
                     "properties": {
                         "process": {
-                            "enum": ["sky130", "gf180", "customer1", "gf130bcd"]
+                            "enum": ["sky130", "gf180", "customer1", "gf130bcd", "ihp_sg13g2"]
                         },
                         "pad_ring": {
                             "enum": ["caravel", "cf20", "pga144"]
diff --git a/chipflow_lib/platforms/sim.py b/chipflow_lib/platforms/sim.py
index 70198a80..ab6412a7 100644
--- a/chipflow_lib/platforms/sim.py
+++ b/chipflow_lib/platforms/sim.py
@@ -68,7 +68,7 @@ def add_monitor(self, inst_type, iface):
             box += '  wire width 1 input 0 \\clk\n'
             for i, ((field_name,), _, field) in enumerate(iface.signature.flatten(iface)):
                 field_width = Shape.cast(field.shape()).width
-                box += f'  wire width {field_width} input {i+1} \\{field_name}\n'
+                box += f'  wire width {field_width} input {i + 1} \\{field_name}\n'
             box += 'end\n\n'
             self.sim_boxes[inst_type] = box
         return Instance(inst_type, **conns)
diff --git a/chipflow_lib/software/soft_gen.py b/chipflow_lib/software/soft_gen.py
index 217c8ae4..50e92528 100644
--- a/chipflow_lib/software/soft_gen.py
+++ b/chipflow_lib/software/soft_gen.py
@@ -51,9 +51,9 @@ def soc_h(self):
             result += f'#define puts(x) uart_puts({uart}, x)\n'
             result += f'#define puthex(x) uart_puthex({uart}, x)\n'
         else:
-            result += f'#define putc(x) do {{ (void)x; }} while(0) \n'
-            result += f'#define puts(x) do {{ (void)x; }} while(0)\n'
-            result += f'#define puthex(x) do {{ (void)x; }} while(0)\n'
+            result += '#define putc(x) do {{ (void)x; }} while(0)\n'
+            result += '#define puts(x) do {{ (void)x; }} while(0)\n'
+            result += '#define puthex(x) do {{ (void)x; }} while(0)\n'
 
         result += "#endif\n"
         return result
@@ -70,7 +70,7 @@ def start(self):
 
 # zero-initialize register file
 addi x1, zero, 0
-li x2, 0x{self.ram_start+self.ram_size:08x} # Top of stack
+li x2, 0x{self.ram_start + self.ram_size:08x} # Top of stack
 addi x3, zero, 0
 addi x4, zero, 0
 addi x5, zero, 0
diff --git a/docs/chipflow-toml-guide.rst b/docs/chipflow-toml-guide.rst
index f358ee40..0990e83e 100644
--- a/docs/chipflow-toml-guide.rst
+++ b/docs/chipflow-toml-guide.rst
@@ -37,18 +37,18 @@ You'll choose the ``process`` and ``pad_ring`` based in the requirements of your
 Available processes
 -------------------
 
-+-----------+------------+---------------------------+
-|| Process  || Supported || Notes                    |
-||          || pad rings ||                          |
-+===========+============+===========================+
-| sky130    | caravel    | Skywater 130nm            |
-+-----------+------------+---------------------------+
-| gf180     | caravel    | GlobalFoundries 180nm     |
-+-----------+------------+---------------------------+
-| gf130bcd  | pga144     | GlobalFoundries 130nm BCD |
-+-----------+------------+---------------------------+
-| customer1 | cf20       | To be announced.          |
-+-----------+------------+---------------------------+
++------------+------------+---------------------------+
+|| Process   || Supported || Notes                    |
+||           || pad rings ||                          |
++============+============+===========================+
+| sky130     | caravel    | Skywater 130nm            |
++------------+------------+---------------------------+
+| gf180      | caravel    | GlobalFoundries 180nm     |
++------------+------------+---------------------------+
+| gf130bcd   | pga144     | GlobalFoundries 130nm BCD |
++------------+------------+---------------------------+
+| ihp_sg13g2 | pga144     | IHP SG13G2 130nm SiGe     |
++------------+------------+---------------------------+
 
 Available pad rings
 -------------------
diff --git a/pyproject.toml b/pyproject.toml
index 6960ae04..d17d51c0 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -16,20 +16,20 @@ authors = [
 ]
 license = {file = "LICENSE.md"}
 
-requires-python = "~=3.8"
+requires-python = ">=3.9"
 dependencies = [
-    "amaranth>=0.5,<0.6",
+    "amaranth>=0.5,<0.7",
     "amaranth-soc @ git+https://github.com/amaranth-lang/amaranth-soc",
     "amaranth-boards @ git+https://github.com/amaranth-lang/amaranth-boards",
     "amaranth-stdio @ git+https://github.com/amaranth-lang/amaranth-stdio",
     "amaranth-orchard @ git+https://github.com/ChipFlow/amaranth-orchard",
-    "yowasp-yosys~=0.41.0.0",
-    "yowasp-nextpnr-ecp5==0.7.0.11.post528.dev0",
+    "yowasp-yosys>=0.41.0.0",
+    "yowasp-nextpnr-ecp5>=0.7",
     "yowasp-runtime",
-    "tomli~=2.0.1",
-    "jsonschema~=4.17.3",
-    "doit~=0.36.0",
-    "requests~=2.30.0",
+    "tomli>=2.0.1",
+    "jsonschema>=4.17.3",
+    "doit>=0.36.0",
+    "requests>=2.30.0",
 ]
 
 [project.scripts]
@@ -45,11 +45,11 @@ build-backend = "pdm.backend"
 
 [tool.pdm.dev-dependencies]
 test = [
-    "pytest~=7.2.0",
+    "pytest>=7.2.0",
     "sphinx>=7.1.2",
 ]
 lint = [
-    "pycodestyle~=2.10.0",
+    "pycodestyle>=2.11",
 ]
 
 [tool.pdm.scripts]