From 9889e9ee75d190168a8bf87a382112b367b211be Mon Sep 17 00:00:00 2001
From: Rob Taylor <rob.taylor@chipflow.io>
Date: Tue, 11 Feb 2025 16:01:08 +0000
Subject: [PATCH 1/6] Update README to use pdm install

---
 README.md | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/README.md b/README.md
index 27fe390f..f64e146b 100644
--- a/README.md
+++ b/README.md
@@ -1,14 +1,12 @@
 # ChipFlow library
 
-WIP
-
+This is a small library to make working with the ChipFlow platform easy and straightforward.
 
 ## Installation and usage
 
 This library uses [PDM](https://pdm.fming.dev/) for dependency management, testing, building, and publishing. Install PDM first. Then run:
 
 ```
-pdm lock
 pdm install
 ```
 

From fc9ea00596143be7e932bc510a0cf3c471970a86 Mon Sep 17 00:00:00 2001
From: Rob Taylor <rob.taylor@chipflow.io>
Date: Tue, 11 Feb 2025 16:10:17 +0000
Subject: [PATCH 2/6] Add pin-lock functionality and remove providers

In order to remove the need for users to define their own SiliconStep
and pin layout.This introduces a number of mechanisms:

 - PinSignature: a mechanism for Components to label wiring that should
   be routed to pads/pins and the requriments.
 - Pin lock mechanism: addition of `pins` subcommand to `chipflow` cli
   tool. This inspects the top level components and maps the ports to
   pins, with pin behaviour defined by the package definition.
 - Package definitions - basis for package definitions in chipflow-lib
 - General purpose SiliconStep

Still remaining follow on changes are:
 - Encoding power, clock, heartbeat and jtag pin locations in package
   definitions.
 - Pin lock for FPGA boards
 - Removal of need for user to define other steps (sim, software, board,
   export verilog)
---
 chipflow_lib/__init__.py              | 142 ++++++++-
 chipflow_lib/cli.py                   | 208 ++++---------
 chipflow_lib/errors.py                |   3 +
 chipflow_lib/pin_lock.py              | 169 +++++++++++
 chipflow_lib/platforms/__init__.py    |   3 +
 chipflow_lib/platforms/silicon.py     | 175 ++++++++---
 chipflow_lib/platforms/sim.py         |   4 -
 chipflow_lib/platforms/utils.py       | 421 ++++++++++++++++++++++++++
 chipflow_lib/providers/__init__.py    |   0
 chipflow_lib/providers/board_ulx3s.py | 150 ---------
 chipflow_lib/providers/silicon.py     | 132 --------
 chipflow_lib/providers/sim.py         |  68 -----
 chipflow_lib/steps/silicon.py         |  85 ++++--
 13 files changed, 989 insertions(+), 571 deletions(-)
 create mode 100644 chipflow_lib/errors.py
 create mode 100644 chipflow_lib/pin_lock.py
 create mode 100644 chipflow_lib/platforms/utils.py
 delete mode 100644 chipflow_lib/providers/__init__.py
 delete mode 100644 chipflow_lib/providers/board_ulx3s.py
 delete mode 100644 chipflow_lib/providers/silicon.py
 delete mode 100644 chipflow_lib/providers/sim.py

diff --git a/chipflow_lib/__init__.py b/chipflow_lib/__init__.py
index 21b1cc91..09adb0ba 100644
--- a/chipflow_lib/__init__.py
+++ b/chipflow_lib/__init__.py
@@ -1,4 +1,144 @@
-# SPDX-License-Identifier: BSD-2-Clause
+import importlib.metadata
+import jsonschema
+import os
+import sys
+import tomli
+
+__version__ = importlib.metadata.version("chipflow_lib")
+
 
 class ChipFlowError(Exception):
     pass
+
+
+def _get_cls_by_reference(reference, context):
+    module_ref, _, class_ref = reference.partition(":")
+    try:
+        module_obj = importlib.import_module(module_ref)
+    except ModuleNotFoundError as e:
+        raise ChipFlowError(f"Module `{module_ref}` referenced by {context} is not found") from e
+    try:
+        return getattr(module_obj, class_ref)
+    except AttributeError as e:
+        raise ChipFlowError(f"Module `{module_ref}` referenced by {context} does not define "
+                          f"`{class_ref}`") from e
+
+
+def _ensure_chipflow_root():
+    if "CHIPFLOW_ROOT" not in os.environ:
+        os.environ["CHIPFLOW_ROOT"] = os.getcwd()
+    if os.environ["CHIPFLOW_ROOT"] not in sys.path:
+        sys.path.append(os.environ["CHIPFLOW_ROOT"])
+    return os.environ["CHIPFLOW_ROOT"]
+
+
+# TODO: convert to pydantic, one truth of source for the schema
+config_schema = {
+    "$schema": "https://json-schema.org/draft/2020-12/schema",
+    "$id": "https://chipflow.io/meta/chipflow.toml.schema.json",
+    "title": "chipflow.toml",
+    "type": "object",
+    "required": [
+        "chipflow"
+    ],
+    "properties": {
+        "chipflow": {
+            "type": "object",
+            "required": [
+                "steps",
+                "silicon"
+            ],
+            "additionalProperties": False,
+            "properties": {
+                "project_name": {
+                    "type": "string",
+                },
+                "top": {
+                    "type": "object",
+                },
+                "steps": {
+                    "type": "object",
+                },
+                "clocks": {
+                    "type": "object",
+                    "patternPropertues": {
+                        ".+": {"type": "string"}
+                    },
+                },
+                "resets": {
+                    "type": "object",
+                    "patternPropertues": {
+                        ".+": {"type": "string"}
+                    },
+                },
+                "silicon": {
+                    "type": "object",
+                    "required": [
+                        "process",
+                        "package",
+                    ],
+                    "additionalProperties": False,
+                    "properties": {
+                        "process": {
+                            "enum": ["sky130", "gf180", "customer1", "gf130bcd", "ihp_sg13g2"]
+                        },
+                        "package": {
+                            "enum": ["caravel", "cf20", "pga144"]
+                        },
+                        "pads": {"$ref": "#/$defs/pin"},
+                        "power": {"$ref": "#/$defs/pin"},
+                        "debug": {
+                            "type": "object",
+                            "properties": {
+                                "heartbeat": {"type": "boolean"}
+                            }
+                        }
+                    },
+                },
+            },
+        },
+    },
+    "$defs": {
+        "pin": {
+            "type": "object",
+            "additionalProperties": False,
+            "minProperties": 1,
+            "patternProperties": {
+                ".+": {
+                    "type": "object",
+                    "required": [
+                        "type",
+                        "loc",
+                    ],
+                    "additionalProperties": False,
+                    "properties": {
+                        "type": {
+                            "enum": ["io", "i", "o", "oe", "clock", "reset", "power", "ground"]
+                        },
+                        "loc": {
+                            "type": "string",
+                            "pattern": "^[NSWE]?[0-9]+$"
+                        },
+                    }
+                }
+            }
+        }
+    }
+}
+
+
+def _parse_config():
+    chipflow_root = _ensure_chipflow_root()
+    config_file = f"{chipflow_root}/chipflow.toml"
+    return _parse_config_file(config_file)
+
+
+def _parse_config_file(config_file):
+    with open(config_file, "rb") as f:
+        config_dict = tomli.load(f)
+
+    try:
+        jsonschema.validate(config_dict, config_schema)
+        return config_dict
+    except jsonschema.ValidationError as e:
+        raise ChipFlowError(f"Syntax error in `chipflow.toml` at `{'.'.join(e.path)}`: {e.message}")
diff --git a/chipflow_lib/cli.py b/chipflow_lib/cli.py
index bf189416..193c4a92 100644
--- a/chipflow_lib/cli.py
+++ b/chipflow_lib/cli.py
@@ -1,173 +1,83 @@
 # SPDX-License-Identifier: BSD-2-Clause
-
-import os
-import sys
-import inspect
-import importlib
 import argparse
-import tomli
-import jsonschema
-
-from . import ChipFlowError
-
-
-def _get_cls_by_reference(reference, context):
-    module_ref, _, class_ref = reference.partition(":")
-    try:
-        module_obj = importlib.import_module(module_ref)
-    except ModuleNotFoundError as e:
-        raise ChipFlowError(f"Module `{module_ref}` referenced by {context} is not found")
-    try:
-        return getattr(module_obj, class_ref)
-    except AttributeError as e:
-        raise ChipFlowError(f"Module `{module_ref}` referenced by {context} does not define "
-                            f"`{class_ref}`") from None
-
-
-def _ensure_chipflow_root():
-    if "CHIPFLOW_ROOT" not in os.environ:
-        os.environ["CHIPFLOW_ROOT"] = os.getcwd()
-    if os.environ["CHIPFLOW_ROOT"] not in sys.path:
-        sys.path.append(os.environ["CHIPFLOW_ROOT"])
-    return os.environ["CHIPFLOW_ROOT"]
+import inspect
+import sys
+import traceback
+import logging
 
+from pprint import pformat
 
-config_schema = {
-    "$schema": "https://json-schema.org/draft/2020-12/schema",
-    "$id": "https://chipflow.io/meta/chipflow.toml.schema.json",
-    "title": "chipflow.toml",
-    "type": "object",
-    "required": [
-        "chipflow"
-    ],
-    "properties": {
-        "chipflow": {
-            "type": "object",
-            "required": [
-                "steps",
-                "silicon"
-            ],
-            "additionalProperties": False,
-            "properties": {
-                "project_id": {
-                    "type": "integer",
-                },
-                "steps": {
-                    "type": "object",
-                },
-                "silicon": {
-                    "type": "object",
-                    "required": [
-                        "process",
-                        "pad_ring",
-                        "pads",
-                    ],
-                    "additionalProperties": False,
-                    "properties": {
-                        "process": {
-                            "enum": ["sky130", "gf180", "customer1", "gf130bcd", "ihp_sg13g2"]
-                        },
-                        "pad_ring": {
-                            "enum": ["caravel", "cf20", "pga144"]
-                        },
-                        "pads": {
-                            "type": "object",
-                            "additionalProperties": False,
-                            "minProperties": 1,
-                            "patternProperties": {
-                                ".+": {
-                                    "type": "object",
-                                    "required": [
-                                        "type",
-                                        "loc",
-                                    ],
-                                    "additionalProperties": False,
-                                    "properties": {
-                                        "type": {
-                                            "enum": ["io", "i", "o", "oe", "clk"]
-                                        },
-                                        "loc": {
-                                            "type": "string",
-                                            "pattern": "^[NSWE]?[0-9]+$"
-                                        },
-                                    }
-                                }
-                            }
-                        },
-                        "power": {
-                            "type": "object",
-                            "additionalProperties": False,
-                            "patternProperties": {
-                                ".+": {
-                                    "type": "object",
-                                    "required": [
-                                        "loc",
-                                    ],
-                                    "additionalProperties": False,
-                                    "properties": {
-                                        "loc": {
-                                            "type": "string",
-                                            "pattern": "^[NSWE]?[0-9]+$"
-                                        },
-                                    }
-                                }
-                            }
-                        },
-                    }
-                },
-            },
-        }
-    }
-}
+from . import (
+    ChipFlowError,
+    _get_cls_by_reference,
+    _parse_config,
+)
+from .pin_lock import PinCommand
 
 
-def _parse_config():
-    chipflow_root = _ensure_chipflow_root()
-    config_file = f"{chipflow_root}/chipflow.toml"
-    return _parse_config_file(config_file)
+logging.basicConfig(stream=sys.stdout, level=logging.WARNING)
 
 
-def _parse_config_file(config_file):
-    with open(config_file, "rb") as f:
-        config_dict = tomli.load(f)
-
-    try:
-        jsonschema.validate(config_dict, config_schema)
-        return config_dict
-    except jsonschema.ValidationError as e:
-        raise ChipFlowError(f"Syntax error in `chipflow.toml` at `{'.'.join(e.path)}`: {e.message}")
+class UnexpectedError(ChipFlowError):
+    pass
 
 
 def run(argv=sys.argv[1:]):
     config = _parse_config()
 
-    steps = {}
+    commands = {}
+    commands["pin"] = PinCommand(config)
+
     for step_name, step_reference in config["chipflow"]["steps"].items():
         step_cls = _get_cls_by_reference(step_reference, context=f"step `{step_name}`")
         try:
-            steps[step_name] = step_cls(config)
+            commands[step_name] = step_cls(config)
         except Exception:
             raise ChipFlowError(f"Encountered error while initializing step `{step_name}` "
-                                f"using `{step_reference}`")
-
-    parser = argparse.ArgumentParser()
-    step_argument = parser.add_subparsers(dest="step", required=True)
-    for step_name, step_cls in steps.items():
-        step_subparser = step_argument.add_parser(step_name, help=inspect.getdoc(step_cls))
+                              f"using `{step_reference}`")
+
+    parser = argparse.ArgumentParser(
+        prog="chipflow",
+        description="Command line tool for interacting with the ChipFlow platform")
+
+    parser.add_argument(
+        "--verbose", "-v",
+        dest="log_level",
+        action="append_const",
+        const=10,
+        help="increase verbosity of messages; can be supplied multiple times to increase verbosity"
+    )
+
+    command_argument = parser.add_subparsers(dest="command", required=True)
+    for command_name, command in commands.items():
+        command_subparser = command_argument.add_parser(command_name, help=inspect.getdoc(command))
         try:
-            step_cls.build_cli_parser(step_subparser)
+            command.build_cli_parser(command_subparser)
         except Exception:
             raise ChipFlowError(f"Encountered error while building CLI argument parser for "
-                                f"step `{step_name}`")
+                              f"step `{command_name}`")
 
+    # each verbose flag increases versbosity (e.g. -v -v, -vv, --verbose --verbose)
+    # cute trick using append_const and summing
     args = parser.parse_args(argv)
-    try:
-        steps[args.step].run_cli(args)
-    except ChipFlowError:
-        raise
-    except Exception:
-        raise ChipFlowError(f"Encountered error while running CLI for step `{args.step}`")
-
+    if args.log_level:
+        log_level = max(logging.DEBUG, logging.WARNING - sum(args.log_level))
+        logging.getLogger().setLevel(log_level)
 
-if __name__ == '__main__':
-    run()
+    try:
+        try:
+            commands[args.command].run_cli(args)
+        except ChipFlowError:
+            raise
+        except Exception as e:
+            # convert to ChipFlowError so all handling is same.
+            raise UnexpectedError(
+                f"Unexpected error, please report to ChipFlow:\n"
+                f"args =\n{pformat(args)}\n"
+                f"traceback =\n{''.join(traceback.format_exception(e))}"
+            ) from e
+    except ChipFlowError as e:
+        cmd = args.command
+        if hasattr(args, "action"):
+            cmd += f" {args.action}"
+        print(f"Error while executing `{cmd}`: {e}")
diff --git a/chipflow_lib/errors.py b/chipflow_lib/errors.py
new file mode 100644
index 00000000..6dcb7917
--- /dev/null
+++ b/chipflow_lib/errors.py
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: BSD-2-Clause
+class ChipFlowError(Exception):
+    pass
diff --git a/chipflow_lib/pin_lock.py b/chipflow_lib/pin_lock.py
new file mode 100644
index 00000000..934f7ad4
--- /dev/null
+++ b/chipflow_lib/pin_lock.py
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: BSD-2-Clause
+import inspect
+import logging
+
+from pprint import pformat
+from pathlib import Path
+from typing import Any, List, Dict, Tuple
+
+from chipflow_lib import _parse_config, ChipFlowError
+from chipflow_lib.platforms import PACKAGE_DEFINITIONS, PIN_ANNOTATION_SCHEMA, top_interfaces
+from chipflow_lib.platforms.utils import LockFile, Package, PortMap, Port
+
+# logging.basicConfig(stream=sys.stdout, level=logging.DEBUG)
+logger = logging.getLogger(__name__)
+
+
+def count_member_pins(name: str, member: Dict[str, Any]) -> int:
+    "Counts the pins from amaranth metadata"
+    logger.debug(
+        f"count_pins {name} {member['type']} "
+        f"{member['annotations'] if 'annotations' in member else 'no annotations'}"
+    )
+    if member['type'] == 'interface' and 'annotations' in member \
+       and PIN_ANNOTATION_SCHEMA in member['annotations']:
+        return member['annotations'][PIN_ANNOTATION_SCHEMA]['width']
+    elif member['type'] == 'interface':
+        width = 0
+        for n, v in member['members'].items():
+            width += count_member_pins('_'.join([name, n]), v)
+        return width
+    elif member['type'] == 'port':
+        return member['width']
+
+
+def allocate_pins(name: str, member: Dict[str, Any], pins: List[str]) -> Tuple[Dict[str, Port], List[str]]:
+    "Allocate pins based of Amaranth member metadata"
+
+    pin_map = {}
+    logger.debug(f"allocate_pins: name={name}, pins={pins}")
+    logger.debug(f"member={pformat(member)}")
+
+    if member['type'] == 'interface' and 'annotations' in member \
+       and PIN_ANNOTATION_SCHEMA in member['annotations']:
+        logger.debug("matched PinSignature {sig}")
+        name = name
+        sig = member['annotations'][PIN_ANNOTATION_SCHEMA]
+        width = sig['width']
+        pin_map[name] = {'pins': pins[0:width],
+                        'direction': sig['direction'],
+                        'type': 'io'}
+        logger.debug(f"added '{name}':{pin_map[name]} to pin_map")
+        return pin_map, pins[width:]
+    elif member['type'] == 'interface':
+        for k, v in member['members'].items():
+            n = '_'.join([name, k])
+            _map, pins = allocate_pins(n, v, pins)
+            pin_map |= _map
+            logger.debug(f"{pin_map},{_map}")
+        return pin_map, pins
+    elif member['type'] == 'port':
+        logger.warning(f"Port '{name}' has no PinSignature, pin allocation likely to be wrong")
+        name = name
+        width = member['width']
+        pin_map[name] = {'pins': pins[0:width],
+                        'direction': member['dir'],
+                        'type': 'io'}
+        logger.debug(f"added '{name}':{pin_map[name]} to pin_map")
+        return pin_map, pins[width:]
+    else:
+        logging.debug(f"Shouldnt get here. member = {member}")
+        assert False
+
+
+def lock_pins() -> None:
+    config = _parse_config()
+    used_pins = set()
+    oldlock = None
+
+    lockfile = Path('pins.lock')
+    if lockfile.exists():
+        json_string = lockfile.read_text()
+        oldlock = LockFile.model_validate_json(json_string)
+
+    print(f"Locking pins: {'using pins.lock' if lockfile.exists() else ''}")
+    package_name = config["chipflow"]["silicon"]["package"]
+
+    if package_name not in PACKAGE_DEFINITIONS:
+        logger.debug(f"Package '{package_name} is unknown")
+    package_type = PACKAGE_DEFINITIONS[package_name]
+
+    package = Package(package_type=package_type)
+    for d in ("pads", "power"):
+        logger.debug(f"Checking [chipflow.silicon.{d}]:")
+        _map = {}
+        for k, v in config["chipflow"]["silicon"][d].items():
+            pin = str(v['loc'])
+            used_pins.add(pin)
+            port = oldlock.package.check_pad(k, v) if oldlock else None
+            if port and port.pins != [pin]:
+                raise ChipFlowError(
+                    f"chipflow.toml conflicts with pins.lock: "
+                    f"{k} had pin {port.pins}, now {[pin]}."
+                )
+            package.add_pad(k, v)
+
+    logger.debug(f'Pins in use: {package_type.sortpins(used_pins)}')
+
+    unallocated = package_type.pins - used_pins
+
+    logger.debug(f"unallocated pins = {package_type.sortpins(unallocated)}")
+
+    _, interfaces = top_interfaces(config)
+
+    logger.debug(f"All interfaces:\n{pformat(interfaces)}")
+
+    port_map = PortMap({})
+    # we try to keep pins together for each interface
+    for component, iface in interfaces.items():
+        for k, v in iface['interface']['members'].items():
+            logger.debug(f"Interface {component}.{k}:")
+            logger.debug(pformat(v))
+            width = count_member_pins(k, v)
+            logger.debug(f"  {k}: total {width} pins")
+            old_ports = oldlock.port_map.get_ports(component, k) if oldlock else None
+            if old_ports:
+                logger.debug(f"  {component}.{k} found in pins.lock, reusing")
+                logger.debug(pformat(old_ports))
+                old_width = sum([len(p.pins) for p in old_ports.values()])
+                if old_width != width:
+                    raise ChipFlowError(
+                        f"top level interface has changed size. "
+                        f"Old size = {old_width}, new size = {width}"
+                    )
+                port_map.add_ports(component, k, old_ports)
+            else:
+                pins = package_type.allocate(unallocated, width)
+                if len(pins) == 0:
+                    raise ChipFlowError("No pins were allocated by {package}")
+                logger.debug(f"allocated range: {pins}")
+                unallocated = unallocated - set(pins)
+                _map, _ = allocate_pins(k, v, pins)
+                port_map.add_ports(component, k, _map)
+
+    newlock = LockFile(package=package, port_map=port_map, metadata=interfaces)
+
+    with open('pins.lock', 'w') as f:
+        f.write(newlock.model_dump_json(indent=2, serialize_as_any=True))
+
+
+class PinCommand:
+    def __init__(self, config):
+        self.config = config
+
+    def build_cli_parser(self, parser):
+        action_argument = parser.add_subparsers(dest="action")
+        action_argument.add_parser(
+            "lock", help=inspect.getdoc(self.lock).splitlines()[0])
+
+    def run_cli(self, args):
+        logger.debug(f"command {args}")
+        if args.action == "lock":
+            self.lock()
+
+    def lock(self):
+        """Lock the pin map for the design.
+
+        Will attempt to reuse previous pin positions.
+        """
+        lock_pins()
diff --git a/chipflow_lib/platforms/__init__.py b/chipflow_lib/platforms/__init__.py
index e69de29b..9cf52f75 100644
--- a/chipflow_lib/platforms/__init__.py
+++ b/chipflow_lib/platforms/__init__.py
@@ -0,0 +1,3 @@
+from .silicon import *
+from .sim import *
+from .utils import *
diff --git a/chipflow_lib/platforms/silicon.py b/chipflow_lib/platforms/silicon.py
index 32eb6c7a..1a32624f 100644
--- a/chipflow_lib/platforms/silicon.py
+++ b/chipflow_lib/platforms/silicon.py
@@ -1,65 +1,114 @@
 # SPDX-License-Identifier: BSD-2-Clause
-
+import logging
 import os
 import subprocess
 
-from amaranth import *
-from amaranth.lib import io
+from dataclasses import dataclass
+
+from amaranth import Module, Signal, Cat, ClockDomain, ClockSignal, ResetSignal
+
+from amaranth.lib import wiring, io
+from amaranth.lib.cdc import FFSynchronizer
+from amaranth.lib.wiring import Component, In
 
 from amaranth.back import rtlil
 from amaranth.hdl import Fragment
 from amaranth.hdl._ir import PortDirection
 
 from .. import ChipFlowError
-
+from .utils import load_pinlock, Port
 
 __all__ = ["SiliconPlatformPort", "SiliconPlatform"]
 
+logger = logging.getLogger(__name__)
+
+
+def make_hashable(cls):
+    def __hash__(self):
+        return hash(id(self))
+
+    def __eq__(self, obj):
+        return id(self) == id(obj)
+
+    cls.__hash__ = __hash__
+    cls.__eq__ = __eq__
+    return cls
+
+
+HeartbeatSignature = wiring.Signature({"heartbeat_i": In(1)})
+
+
+@make_hashable
+@dataclass
+class Heartbeat(Component):
+    clock_domain: str = "sync"
+    counter_size: int = 23
+    name: str = "heartbeat"
+
+    def __init__(self, ports):
+        super().__init__(HeartbeatSignature)
+        self.ports = ports
+
+    def elaborate(self, platform):
+        m = Module()
+        # Heartbeat LED (to confirm clock/reset alive)
+        heartbeat_ctr = Signal(self.counter_size)
+        getattr(m.d, self.clock_domain).__iadd__(heartbeat_ctr.eq(heartbeat_ctr + 1))
+
+        heartbeat_buffer = io.Buffer("o", self.ports.heartbeat)
+        m.submodules.heartbeat_buffer = heartbeat_buffer
+        m.d.comb += heartbeat_buffer.o.eq(heartbeat_ctr[-1])
+        return m
+
 
 class SiliconPlatformPort(io.PortLike):
-    def __init__(self, name, direction, width, *, invert=False):
-        if not isinstance(name, str):
-            raise TypeError(f"Name must be a string, not {name!r}")
-        if not (isinstance(width, int) and width >= 0):
-            raise TypeError(f"Width must be a non-negative integer, not {width!r}")
-        if not isinstance(invert, bool):
-            raise TypeError(f"'invert' must be a bool, not {invert!r}")
-
-        self._direction = io.Direction(direction)
+    def __init__(self,
+                 component: str,
+                 name: str,
+                 port: Port,
+                 *,
+                 invert: bool = False):
+        self._direction = io.Direction(port.direction)
         self._invert = invert
 
-        self._i = self._o = self._oe = None
+        self._i = self._o = self._oe = Signal(1)
         if self._direction in (io.Direction.Input, io.Direction.Bidir):
-            self._i = Signal(width, name=f"{name}__i")
+            self._i = Signal(port.width, name=f"{component}_{name}__i")
         if self._direction in (io.Direction.Output, io.Direction.Bidir):
-            self._o = Signal(width, name=f"{name}__o")
-            self._oe = Signal(width, name=f"{name}__oe")
+            self._o = Signal(port.width, name=f"{component}_{name}__o")
+            self._oe = Signal(1, name=f"{component}_{name}__oe")
+        self._pins = port.pins
+        logger.debug(f"Created SiliconPlatformPort {name}, width={len(port.pins)},dir{self._direction}")
 
     @property
     def i(self):
         if self._i is None:
             raise AttributeError("SiliconPlatformPort with output direction does not have an "
-                                 "input signal")
+                               "input signal")
         return self._i
 
     @property
     def o(self):
         if self._o is None:
             raise AttributeError("SiliconPlatformPort with input direction does not have an "
-                                 "output signal")
+                               "output signal")
         return self._o
 
     @property
     def oe(self):
         if self._oe is None:
             raise AttributeError("SiliconPlatformPort with input direction does not have an "
-                                 "output enable signal")
+                               "output enable signal")
         return self._oe
 
     @property
     def direction(self):
         return self._direction
 
+    @property
+    def pins(self):
+        return self._pins
+
     @property
     def invert(self):
         return self._invert
@@ -73,7 +122,7 @@ def __len__(self):
         if self._direction is io.Direction.Bidir:
             assert len(self._i) == len(self._o) == len(self._oe)
             return len(self._i)
-        assert False # :nocov:
+        assert False  # :nocov:
 
     def __getitem__(self, key):
         result = object.__new__(type(self))
@@ -103,6 +152,11 @@ def __add__(self, other):
         result._direction = direction
         return result
 
+    def __repr__(self):
+        return (f"SiliconPlatformPort(direction={repr(self._direction)}, width={len(self)}, "
+                f"i={repr(self._i)}, o={repr(self._o)}, oe={repr(self._oe)}, "
+                f"invert={repr(self._invert)})")
+
 
 class IOBuffer(io.Buffer):
     def elaborate(self, platform):
@@ -160,39 +214,58 @@ def elaborate(self, platform):
 
 
 class SiliconPlatform:
-    def __init__(self, pads):
-        self._pads = pads
+    def __init__(self, config):
+        self._config = config
         self._ports = {}
         self._files = {}
 
-    def request(self, name):
+    def instantiate_ports(self, m: Module):
+        if hasattr(self, "pinlock"):
+            return
+
+        pinlock = load_pinlock()
+        for component, iface in pinlock.port_map.items():
+            for k, v in iface.items():
+                for name, port in v.items():
+                    self._ports[name] = SiliconPlatformPort(component, name, port)
+
+        for clock, name in self._config["chipflow"]["clocks"].items():
+            if name not in pinlock.package.clocks:
+                raise ChipFlowError("Unable to find clock {name} in pinlock")
+
+            port_data = pinlock.package.clocks[name]
+            port = SiliconPlatformPort(component, name, port_data, invert=True)
+            self._ports[name] = port
+            if clock == 'default':
+                clock = 'sync'
+            setattr(m.domains, clock, ClockDomain(name=clock))
+            clk_buffer = io.Buffer("i", port)
+            setattr(m.submodules, "clk_buffer_" + clock, clk_buffer)
+            m.d.comb += ClockSignal().eq(clk_buffer.i)
+
+        for reset, name in self._config["chipflow"]["resets"].items():
+            port_data = pinlock.package.resets[name]
+            port = SiliconPlatformPort(component, name, port_data)
+            self._ports[name] = port
+            rst_buffer = io.Buffer("i", port)
+            setattr(m.submodules, reset, rst_buffer)
+            setattr(m.submodules, reset + "_sync", FFSynchronizer(rst_buffer.i, ResetSignal()))
+
+        self.pinlock = pinlock
+
+    def request(self, name=None, **kwargs):
         if "$" in name:
             raise NameError(f"Reserved character `$` used in pad name `{name}`")
-        if name not in self._pads:
-            raise NameError(f"Pad `{name}` is not defined in chipflow.toml")
-        if name in self._ports:
-            raise NameError(f"Pad `{name}` has already been requested")
-
-        pad_type = self._pads[name]["type"]
-        # `clk` is used for clock tree synthesis, but treated as `i` in frontend
-        if pad_type in ("i", "clk"):
-            direction = io.Direction.Input
-        elif pad_type in ("o", "oe"):
-            direction = io.Direction.Output
-        elif pad_type == "io":
-            direction = io.Direction.Bidir
-        else:
-            assert False
-
-        self._ports[name] = port = SiliconPlatformPort(name, direction, 1)
-        return port
+        if name not in self._ports:
+            raise NameError(f"Pad `{name}` is not present in the pin lock")
+        return self._ports[name]
 
     def get_io_buffer(self, buffer):
         if isinstance(buffer, io.Buffer):
             result = IOBuffer(buffer.direction, buffer.port)
         elif isinstance(buffer, io.FFBuffer):
             result = FFBuffer(buffer.direction, buffer.port,
-                              i_domain=buffer.i_domain, o_domain=buffer.o_domain)
+                            i_domain=buffer.i_domain, o_domain=buffer.o_domain)
         else:
             raise TypeError(f"Unsupported buffer type {buffer!r}")
 
@@ -215,7 +288,7 @@ def add_file(self, filename, content):
     def _check_clock_domains(self, fragment, sync_domain=None):
         for clock_domain in fragment.domains.values():
             if clock_domain.name != "sync" or (sync_domain is not None and
-                                               clock_domain is not sync_domain):
+                                             clock_domain is not sync_domain):
                 raise ChipFlowError("Only a single clock domain, called 'sync', may be used")
             sync_domain = clock_domain
 
@@ -252,10 +325,10 @@ def build(self, elaboratable, name="top"):
             filename_b = filename.encode("utf-8")
             if filename.endswith(".v") or filename.endswith(".vh"):
                 yosys_script.append(b"read_verilog -defer <<" + filename_b + b"\n" +
-                                    content + b"\n" + filename_b)
+                                  content + b"\n" + filename_b)
             elif filename.endswith(".sv"):
                 yosys_script.append(b"read_verilog -defer -sv <<" + filename_b + b"\n" +
-                                    content + b"\n" + filename_b)
+                                  content + b"\n" + filename_b)
             else:
                 raise ValueError(f"File `{filename}` is not supported by the build platform")
         yosys_script += [
@@ -275,3 +348,13 @@ def build(self, elaboratable, name="top"):
             "-o", output_rtlil.replace("\\", "/")
         ])
         return output_rtlil
+
+    def default_clock(m, platform, clock, reset):
+        # Clock generation
+        m.domains.sync = ClockDomain()
+
+        clk = platform.request(clock)
+        m.d.comb += ClockSignal().eq(clk.i)
+        m.submodules.rst_sync = FFSynchronizer(
+            ~platform.request(reset).i,
+            ResetSignal())
diff --git a/chipflow_lib/platforms/sim.py b/chipflow_lib/platforms/sim.py
index 19d5540e..d87286d5 100644
--- a/chipflow_lib/platforms/sim.py
+++ b/chipflow_lib/platforms/sim.py
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
-import argparse
-import sys
 import os
 from pathlib import Path
 
@@ -13,8 +11,6 @@
 
 
 class SimPlatform:
-    from ..providers import sim as providers
-
     def __init__(self):
         self.build_dir = os.path.join(os.environ['CHIPFLOW_ROOT'], 'build', 'sim')
         self.extra_files = dict()
diff --git a/chipflow_lib/platforms/utils.py b/chipflow_lib/platforms/utils.py
new file mode 100644
index 00000000..c8bcbe6b
--- /dev/null
+++ b/chipflow_lib/platforms/utils.py
@@ -0,0 +1,421 @@
+import abc
+import enum
+import itertools
+import logging
+import pathlib
+import pydantic
+
+from collections import OrderedDict, deque
+from collections.abc import MutableMapping
+from pprint import pformat
+from typing import Set, List, Dict, Optional, Union, Literal
+
+from amaranth.lib import wiring, io, meta
+from amaranth.lib.wiring import In, Out
+from pydantic import BaseModel, ConfigDict
+
+from .. import ChipFlowError, _ensure_chipflow_root, _get_cls_by_reference
+
+
+__all__ = ['PIN_ANNOTATION_SCHEMA', 'PinSignature',
+           'OutputPinSignature', 'InputPinSignature', 'BidirPinSignature',
+           'load_pinlock', "PACKAGE_DEFINITIONS", 'top_interfaces']
+
+
+logger = logging.getLogger(__name__)
+
+
+def _chipflow_schema_uri(name: str, version: int) -> str:
+    return f"https://api.chipflow.com/schemas/{version}/{name}"
+
+
+class _PinAnnotationModel(BaseModel):
+    model_config = ConfigDict(use_enum_values=True)
+    direction: io.Direction
+    width: int
+
+    @classmethod
+    def _annotation_schema(cls):
+        schema = _PinAnnotationModel.model_json_schema()
+        schema['$schema'] = "https://json-schema.org/draft/2020-12/schema"
+        schema['$id'] = _chipflow_schema_uri("pin-annotation", 0)
+        return schema
+
+    def __init__(self, **kwargs):
+        kwargs['url'] = _chipflow_schema_uri("pin-annotation", 0)
+        super().__init__(**kwargs)
+
+
+class _PinAnnotation(meta.Annotation):
+    schema = _PinAnnotationModel._annotation_schema()
+
+    def __init__(self, **kwargs):
+        self.model = _PinAnnotationModel(**kwargs)
+
+    @property
+    def origin(self):  # type: ignore
+        return self.model
+
+    def as_json(self):  # type: ignore
+        return self.model.model_dump()
+
+
+PIN_ANNOTATION_SCHEMA = str(_chipflow_schema_uri("pin-annotation", 0))
+
+
+class PinSignature(wiring.Signature):
+    """Amaranth Signtaure used to decorate wires that would
+    usually be brought out onto a pin on the package.
+    """
+
+    def __init__(self, direction, width=1, init=None):
+        self._direction = direction
+        self._width = width
+        self._init = init
+        match direction:
+            case io.Direction.Bidir:
+                sig = {
+                    "o": Out(width),
+                    "oe": Out(1),
+                    "i": In(width)
+                }
+            case io.Direction.Input:
+                sig = {"i": In(width)}
+            case io.Direction.Output:
+                sig = {"o": Out(width)}
+            case _:
+                assert False
+
+        super().__init__(sig)
+
+    def annotations(self, *args):
+        annotations = wiring.Signature.annotations(self, *args)
+        pin_annotation = _PinAnnotation(direction=self._direction, width=self._width)
+        return annotations + (pin_annotation,)
+
+    def __repr__(self):
+        return f"PinSignature({self._direction}, {self._width})"
+
+
+def OutputPinSignature(width, **kwargs):
+    return PinSignature(io.Direction.Output, width=width, **kwargs)
+
+
+def InputPinSignature(width, **kwargs):
+    return PinSignature(io.Direction.Input, width=width, **kwargs)
+
+
+def BidirPinSignature(width, **kwargs):
+    return PinSignature(io.Direction.Bidir, width=width, **kwargs)
+
+
+Pin = Union[tuple, str]
+PinSet = Set[Pin]
+PinList = List[Pin]
+Pins = Union[PinSet, PinList]
+
+
+class _Side(enum.IntEnum):
+    N = 1
+    E = 2
+    S = 3
+    W = 4
+
+    def __str__(self):
+        return f'{self.name}'
+
+
+def _group_consecutive_items(ordering: PinList, lst: PinList) -> OrderedDict[int, List[PinList]]:
+    if not lst:
+        return {}
+
+    grouped = []
+    last = lst[0]
+    current_group = [last]
+
+    logger.debug(f"_group_consecutive_items starting with {current_group}")
+
+    for item in lst[1:]:
+        idx = ordering.index(last)
+        next = ordering[idx + 1] if idx < len(ordering) - 1 else None
+        logger.debug(f"inspecting {item}, index {idx}, next {next}")
+        if item == next:
+            current_group.append(item)
+            logger.debug("found consecutive, adding to current group")
+        else:
+            logger.debug("found nonconsecutive, creating new group")
+            grouped.append(current_group)
+            current_group = [item]
+        last = item
+
+    grouped.append(current_group)
+    d = {}
+    for g in grouped:
+        # logger.debug(f"adding to group {len(g)} pins {g}")
+        d.setdefault(len(g), []).append(g)
+    return d
+
+
+def _find_contiguous_sequence(ordering: PinList, lst: PinList, total: int) -> PinList:
+    """Find the next sequence of n consecutive numbers in a sorted list
+
+    Args:
+        lst: Sorted list of numbers
+        n: Length of consecutive sequence to find
+
+    Returns:
+        A slice indexing the first sequence of n consecutive numbers found within the given list
+        if unable to find a consecutive list, allocate as contigously as possible
+    """
+    if not lst or len(lst) < total:
+        raise ChipFlowError("Invalid request to find_contiguous_argument")
+
+    grouped = _group_consecutive_items(ordering, lst)
+
+    ret = []
+    n = total
+
+    # start with longest contiguous section, then continue into following sections
+    keys = deque(grouped.keys())
+    best = max(keys)
+    start = keys.index(best)
+    keys.rotate(start)
+
+    for k in keys:
+        for g in grouped[k]:
+            assert n + len(ret) == total
+            if k >= n:
+                ret += g[0:min(n, k)]
+                return ret
+            else:
+                n = n - k
+                ret += g[0:k]
+
+    return ret
+
+
+class _BasePackageDef(pydantic.BaseModel, abc.ABC):
+    """
+    Abstract base class for the definition of a package
+    """
+    # Used by pydantic to differentate when deserialising,
+    # override appropriately when you subclass
+    type: Literal["_BasePackageDef"] = "_BasePackageDef"
+    name: str
+
+    @property
+    @abc.abstractmethod
+    def pins(self) -> PinSet:
+        ...
+
+    @abc.abstractmethod
+    def allocate(self, available: PinSet, width: int) -> PinList:
+        ...
+
+    def to_string(pins: Pins):
+        return [''.join(map(str, t)) for t in pins]
+
+    def sortpins(self, pins: Pins) -> PinList:
+        return list(pins).sort()
+
+
+class _BareDiePackageDef(_BasePackageDef):
+    """Definition of a package with pins on four sides, labelled north, south, east, west
+    with an integer identifier within each side.
+    """
+
+    # Used by pydantic to differentate when deserialising
+    type: Literal["_QuadPackageDef"] = "_QuadPackageDef"
+
+    width: int
+    height: int
+
+    def model_post_init(self, __context):
+        self._ordered_pins = sorted(
+            list(itertools.product((_Side.N, _Side.S), range(self.width))) +
+            list(itertools.product((_Side.W, _Side.E), range(self.height))))
+        return super().model_post_init(__context)
+
+    @property
+    def pins(self) -> PinSet:
+        return set(self._ordered_pins)
+
+    def allocate(self, available: PinSet, width: int) -> PinList:
+        avail_n = self.sortpins(available)
+        logger.debug(f"_BareDiePackageDef.allocate {width} from {len(avail_n)} remaining")
+        ret = _find_contiguous_sequence(self._ordered_pins, avail_n, width)
+        logger.debug(f"_BareDiePackageDef.returned {ret}")
+        assert len(ret) == width
+        return ret
+
+
+class _QuadPackageDef(_BasePackageDef):
+    """Definiton of a PGA package with `size` pins
+
+    This is package with `size` pins, numbered, with the assumption that adjacent pins
+    are numbered close together.
+    """
+
+    # Used by pydantic to differentate when deserialising
+    type: Literal["_PGAPackageDef"] = "_PGAPackageDef"
+
+    width:int
+    height: int
+
+    def model_post_init(self, __context):
+        self._ordered_pins = sorted(
+            [str(i) for i in range(1, self.width * 2 + self.height * 2)])
+        return super().model_post_init(__context)
+
+
+    @property
+    def pins(self) -> PinSet:
+        return set(self._ordered_pins)
+
+    def allocate(self, available: Set[str], width: int) -> List[str]:
+        avail_n = sorted(available)
+        logger.debug(f"QuadPackageDef.allocate {width} from {len(avail_n)} remaining: {available}")
+        ret = _find_contiguous_sequence(self._ordered_pins, avail_n, width)
+        logger.debug(f"QuadPackageDef.returned {ret}")
+        assert len(ret) == width
+        return ret
+
+    def sortpins(self, pins: Union[List[str], Set[str]]) -> List[str]:
+        return sorted(list(pins), key=int)
+
+
+# Add any new package types to both PACKAGE_DEFINITIONS and the PackageDef union
+PACKAGE_DEFINITIONS = {
+    "pga144": _QuadPackageDef(name="pga144", width=36, height=36),
+    "cf20": _BareDiePackageDef(name="cf20", width=7, height=3)
+}
+
+PackageDef = Union[_QuadPackageDef, _BasePackageDef]
+
+
+class Port(pydantic.BaseModel):
+    type: str
+    pins: List[str]
+    direction: Optional[str] = None
+
+    @property
+    def width(self):
+        return len(self.pins)
+
+
+class Package(pydantic.BaseModel):
+    package_type: PackageDef = pydantic.Field(discriminator="type")
+    power: Dict[str, Port] = {}
+    clocks: Dict[str, Port] = {}
+    resets: Dict[str, Port] = {}
+
+    def check_pad(self, name: str, defn: dict):
+        match defn:
+            case {"type": "clock"}:
+                return self.clocks[name] if name in self.clocks else None
+            case {"type": "reset"}:
+                return self.resets[name] if name in self.clocks else None
+            case {"type": "power"}:
+                return self.power[name] if name in self.power else None
+            case {"type": "ground"}:
+                return self.power[name] if name in self.power else None
+            case _:
+                return None
+
+    def add_pad(self, name: str, defn: dict):
+        match defn:
+            case {"type": "clock", "loc": loc}:
+                self.clocks[name] = Port(type="clock", pins=[loc], direction=io.Direction.Input)
+            case {"type": "reset", "loc": loc}:
+                self.resets[name] = Port(type="reset", pins=[loc], direction=io.Direction.Input)
+            case {"type": "power", "loc": loc}:
+                self.power[name] = Port(type="power", pins=[loc])
+            case {"type": "ground", "loc": loc}:
+                self.power[name] = Port(type="ground", pins=[loc])
+            case _:
+                pass
+
+
+_Interface = Dict[str, Dict[str, Port]]
+
+
+class PortMap(pydantic.RootModel[Dict[str, _Interface]], MutableMapping):
+    def __getitem__(self, key: str):
+        return self.root[key]
+
+    def __setitem__(self, key: str, value: _Interface):
+        self.root[key] = value
+
+    def __delitem__(self, key):
+        del self.root[key]
+
+    def __iter__(self):
+        return iter(self.root)
+
+    def __len__(self):
+        return len(self.root)
+
+    def add_port(self, component: str, interface: str, port_name: str, port: Port):
+        if component not in self:
+            self[component] = {}
+        if interface not in self[component]:
+            self[component][interface] = {}
+        self[component][interface][port_name] = port
+
+    def add_ports(self, component: str, interface: str, ports: Dict[str, Port]):
+        if component not in self:
+            self[component] = {}
+        self[component][interface] = ports
+
+    def get_ports(self, component: str, name: str) -> Dict[str, Port]:
+        if component not in self:
+            return None
+        return self[component][name]
+
+
+class LockFile(pydantic.BaseModel):
+    """
+    Representation of a pin lock file.
+
+    Attributes:
+        package: Information about package, power, clocks, reset etc
+        port_map: Mapping of components to interfaces to port
+        metadata: Amaranth metadata, for reference
+    """
+    package: Package
+    port_map: PortMap
+    metadata: dict
+
+
+def load_pinlock():
+    chipflow_root = _ensure_chipflow_root()
+    lockfile = pathlib.Path(chipflow_root, 'pins.lock')
+    if lockfile.exists():
+        json = lockfile.read_text()
+        return LockFile.model_validate_json(json)
+    raise ChipFlowError("Lockfile pins.lock not found. Run `chipflow pin lock`")
+
+
+def top_interfaces(config):
+    interfaces = {}
+    top_components = config["chipflow"]["top"].items()
+    component_configs = {}
+    top = {}
+
+    for name, conf in top_components:
+        if '.' in name:
+            assert conf is dict
+            logger.debug("Config found for {name}")
+            component_configs[name.split('.')[0]] = conf
+
+    for name, ref in top_components:
+        cls = _get_cls_by_reference(ref, context=f"top component: {name}")
+        if name in component_configs:
+            top[name] = cls(component_configs[name])
+        else:
+            top[name] = cls()
+        logger.debug(f"top members for {name}:\n{pformat(top[name].metadata.origin.signature.members)}")
+        # logger.debug(f"adding\n'{name}':{pformat(top[name].metadata.as_json())} to interfaces")
+        interfaces[name] = top[name].metadata.as_json()
+
+    return top, interfaces
diff --git a/chipflow_lib/providers/__init__.py b/chipflow_lib/providers/__init__.py
deleted file mode 100644
index e69de29b..00000000
diff --git a/chipflow_lib/providers/board_ulx3s.py b/chipflow_lib/providers/board_ulx3s.py
deleted file mode 100644
index 7c38c008..00000000
--- a/chipflow_lib/providers/board_ulx3s.py
+++ /dev/null
@@ -1,150 +0,0 @@
-# SPDX-License-Identifier: BSD-2-Clause
-
-from amaranth import *
-from amaranth_boards.ulx3s import *
-from amaranth.lib.cdc import ResetSynchronizer
-from amaranth.lib import io, wiring
-from amaranth.lib.wiring import In
-
-from amaranth_soc import gpio
-
-from amaranth_orchard.memory.spimemio import QSPIPins
-from amaranth_orchard.io.uart import UARTPins
-from amaranth_orchard.memory.hyperram import HyperRAMPins
-
-
-class QSPIFlashProvider(Elaboratable):
-    def __init__(self):
-        self.pins = QSPIPins()
-
-    def elaborate(self, platform):
-        m = Module()
-
-        flash = platform.request("spi_flash", dir=dict(cs='-', copi='-', cipo='-', wp='-', hold='-'))
-        # Flash clock requires a special primitive to access in ECP5
-        m.submodules.usrmclk = Instance(
-            "USRMCLK",
-            i_USRMCLKI=self.pins.clk_o,
-            i_USRMCLKTS=ResetSignal(),  # tristate in reset for programmer accesss
-            a_keep=1,
-        )
-        # IO pins and buffers
-        m.submodules += Instance(
-            "OBZ",
-            o_O=flash.cs.io,
-            i_I=self.pins.csn_o,
-            i_T=ResetSignal(),
-        )
-        # Pins in order
-        data_pins = ["copi", "cipo", "wp", "hold"]
-
-        for i in range(4):
-            m.submodules += Instance(
-                "BB",
-                io_B=getattr(flash, data_pins[i]).io,
-                i_I=self.pins.d_o[i],
-                i_T=~self.pins.d_oe[i],
-                o_O=self.pins.d_i[i]
-            )
-        return m
-
-
-class LEDGPIOProvider(wiring.Component):
-    pins: In(gpio.PinSignature()).array(8)
-
-    def elaborate(self, platform):
-        m = Module()
-        for i in range(8):
-            led = io.Buffer("o", platform.request("led", i, dir="-"))
-            m.submodules[f"led_{i}"] = led
-            m.d.comb += led.o.eq(self.pins[i].o)
-        return m
-
-
-class ButtonGPIOProvider(wiring.Component):
-    pins: In(gpio.PinSignature()).array(2)
-
-    def elaborate(self, platform):
-        m = Module()
-        for i in range(2):
-            btn = io.Buffer("i", platform.request("button_fire", i, dir="-"))
-            m.submodules[f"btn_{i}"] = btn
-            m.d.comb += self.pins[i].i.eq(btn.i)
-        return m
-
-
-class UARTProvider(Elaboratable):
-    def __init__(self):
-        self.pins = UARTPins()
-
-    def elaborate(self, platform):
-        m = Module()
-        uart_pins = platform.request("uart", 0, dir=dict(rx="-", tx="-", rts="-", dtr="-"))
-        m.submodules.uart_rx = uart_rx = io.Buffer("i", uart_pins.rx)
-        m.submodules.uart_tx = uart_tx = io.Buffer("o", uart_pins.tx)
-        m.d.comb += [
-            uart_tx.o.eq(self.pins.tx_o),
-            self.pins.rx_i.eq(uart_rx.i),
-        ]
-        return m
-
-
-class HyperRAMProvider(Elaboratable):
-    def __init__(self):
-        self.pins = HyperRAMPins(cs_count=4)
-
-    def elaborate(self, platform):
-        # Dual HyperRAM PMOD, starting at GPIO 0+/-
-        platform.add_resources([
-            Resource(
-                "hyperram",
-                0,
-                Subsignal("csn",    Pins("9- 9+ 10- 10+", conn=("gpio", 0), dir='o')),
-                Subsignal("rstn",   Pins("8+", conn=("gpio", 0), dir='o')),
-                Subsignal("clk",    Pins("8-", conn=("gpio", 0), dir='o')),
-                Subsignal("rwds",   Pins("7+", conn=("gpio", 0), dir='io')),
-
-                Subsignal("dq",     Pins("3- 2- 1- 0- 0+ 1+ 2+ 3+", conn=("gpio", 0), dir='io')),
-
-                Attrs(IO_TYPE="LVCMOS33"),
-            )
-        ])
-
-        hyperram = platform.request("hyperram", 0)
-
-        m = Module()
-        m.d.comb += [
-            hyperram.clk.o.eq(self.pins.clk_o),
-            hyperram.csn.o.eq(self.pins.csn_o),
-            hyperram.rstn.o.eq(self.pins.rstn_o),
-
-            hyperram.rwds.o.eq(self.pins.rwds_o),
-            hyperram.rwds.oe.eq(self.pins.rwds_oe),
-            self.pins.rwds_i.eq(hyperram.rwds.i),
-
-            hyperram.dq.o.eq(self.pins.dq_o),
-            hyperram.dq.oe.eq(self.pins.dq_oe),
-            self.pins.dq_i.eq(hyperram.dq.i),
-        ]
-        return m
-
-
-class JTAGProvider(Elaboratable):
-    def __init__(self, cpu):
-        pass
-
-    def elaborate(self, platform):
-        return Module()  # JTAG is not connected anywhere
-
-
-class ClockResetProvider(Elaboratable):
-    def __init__(self):
-        pass
-
-    def elaborate(self, platform):
-        m = Module()
-        m.submodules.clk25 = clk25 = io.Buffer("i", platform.request("clk25", dir="-"))
-        m.d.comb += ClockSignal("sync").eq(clk25.i)
-        m.submodules.btn_pwr = btn_pwr = io.Buffer("i", platform.request("button_pwr", dir="-"))
-        m.submodules += ResetSynchronizer(btn_pwr.i, domain="sync")
-        return m
diff --git a/chipflow_lib/providers/silicon.py b/chipflow_lib/providers/silicon.py
deleted file mode 100644
index 71e04293..00000000
--- a/chipflow_lib/providers/silicon.py
+++ /dev/null
@@ -1,132 +0,0 @@
-# SPDX-License-Identifier: BSD-2-Clause
-
-from amaranth import *
-from amaranth.lib.cdc import FFSynchronizer
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In
-
-from amaranth_soc import gpio
-
-from amaranth_orchard.memory.spimemio import QSPIPins
-from amaranth_orchard.io.uart import UARTPins
-from amaranth_orchard.memory.hyperram import HyperRAMPins
-
-
-class QSPIFlashProvider(Elaboratable):
-    def __init__(self):
-        self.pins = QSPIPins()
-
-    def elaborate(self, platform):
-        m = Module()
-        m.d.comb += [
-            platform.request("flash_clk").o.eq(self.pins.clk_o),
-            platform.request("flash_csn").o.eq(self.pins.csn_o),
-        ]
-        for index in range(4):
-            pin = platform.request(f"flash_d{index}")
-            m.d.comb += [
-                self.pins.d_i[index].eq(pin.i),
-                pin.o.eq(self.pins.d_o[index]),
-                pin.oe.eq(self.pins.d_oe[index])
-            ]
-        return m
-
-
-class LEDGPIOProvider(wiring.Component):
-    pins: In(gpio.PinSignature()).array(8)
-
-    def elaborate(self, platform):
-        m = Module()
-        for index in range(8):
-            pin = platform.request(f"gpio_{index}")
-            m.d.comb += [
-                self.pins[index].i.eq(pin.i),
-                pin.o.eq(self.pins[index].o),
-                pin.oe.eq(self.pins[index].oe),
-            ]
-        return m
-
-
-class ButtonGPIOProvider(wiring.Component):
-    pins: In(gpio.PinSignature()).array(2)
-
-    def elaborate(self, platform):
-        m = Module()
-        for index in range(2):
-            pin = platform.request(f"btn_{index}")
-            m.d.comb += [
-                self.pins[index].i.eq(pin.i),
-                pin.o.eq(self.pins[index].o),
-                pin.oe.eq(self.pins[index].oe),
-            ]
-        return m
-
-
-class UARTProvider(Elaboratable):
-    def __init__(self):
-        self.pins = UARTPins()
-
-    def elaborate(self, platform):
-        m = Module()
-        m.d.comb += [
-            platform.request("uart_tx").o.eq(self.pins.tx_o),
-            self.pins.rx_i.eq(platform.request("uart_rx").i),
-        ]
-        return m
-
-
-class HyperRAMProvider(Elaboratable):
-    def __init__(self):
-        self.pins = HyperRAMPins(cs_count=4)
-
-    def elaborate(self, platform):
-        m = Module()
-        m.d.comb += [
-            platform.request("ram_clk").o.eq(self.pins.clk_o),
-            platform.request("ram_rstn").o.eq(self.pins.rstn_o),
-        ]
-
-        for index in range(4):
-            platform.request(f"ram_csn_{index}").o.eq(self.pins.csn_o[index]),
-
-        rwds = platform.request("ram_rwds")
-        m.d.comb += [
-            rwds.o.eq(self.pins.rwds_o),
-            rwds.oe.eq(self.pins.rwds_oe),
-            self.pins.rwds_i.eq(rwds.i),
-        ]
-
-        for index in range(8):
-            dq = platform.request(f"ram_dq_{index}")
-            m.d.comb += [
-                dq.o.eq(self.pins.dq_o[index]),
-                dq.oe.eq(self.pins.dq_oe[index]),
-                self.pins.dq_i[index].eq(dq.i),
-            ]
-
-        return m
-
-
-class JTAGProvider(Elaboratable):
-    def __init__(self, cpu):
-        self.cpu = cpu
-
-    def elaborate(self, platform):
-        m = Module()
-        m.d.comb += [
-            self.cpu.jtag_tck.eq(platform.request("jtag_tck").i),
-            self.cpu.jtag_tdi.eq(platform.request("jtag_tdi").i),
-            self.cpu.jtag_tms.eq(platform.request("jtag_tms").i),
-            platform.request("jtag_tdo").o.eq(self.cpu.jtag_tdo),
-        ]
-        return m
-
-
-class ClockResetProvider(Elaboratable):
-    def elaborate(self, platform):
-        m = Module()
-        m.d.comb += ClockSignal("sync").eq(platform.request("sys_clk").i)
-        m.submodules.rst_sync = FFSynchronizer(
-            ~platform.request("sys_rstn").i,
-            ResetSignal("sync"))
-        return m
diff --git a/chipflow_lib/providers/sim.py b/chipflow_lib/providers/sim.py
deleted file mode 100644
index bdf9bef2..00000000
--- a/chipflow_lib/providers/sim.py
+++ /dev/null
@@ -1,68 +0,0 @@
-# SPDX-License-Identifier: BSD-2-Clause
-
-from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In
-
-from amaranth_soc import gpio
-
-from amaranth_orchard.memory.spimemio import QSPIPins
-from amaranth_orchard.io.uart import UARTPins
-from amaranth_orchard.memory.hyperram import HyperRAMPins
-
-
-class QSPIFlashProvider(Elaboratable):
-    def __init__(self):
-        self.pins = QSPIPins()
-
-    def elaborate(self, platform):
-        return platform.add_model("spiflash_model", self.pins, edge_det=['clk_o', 'csn_o'])
-
-
-class LEDGPIOProvider(wiring.Component):
-    pins: In(gpio.PinSignature()).array(8)
-
-    def elaborate(self, platform):
-        return Module()
-
-
-class ButtonGPIOProvider(wiring.Component):
-    pins: In(gpio.PinSignature()).array(2)
-
-    def elaborate(self, platform):
-        m = Module()
-        for i in range(2):
-            m.d.comb += self.pins[i].i.eq(platform.buttons[i])
-        return m
-
-
-class UARTProvider(Elaboratable):
-    def __init__(self):
-        self.pins = UARTPins()
-
-    def elaborate(self, platform):
-        return platform.add_model("uart_model", self.pins, edge_det=[])
-
-
-class HyperRAMProvider(Elaboratable):
-    def __init__(self):
-        self.pins = HyperRAMPins(cs_count=4)
-
-    def elaborate(self, platform):
-        return platform.add_model("hyperram_model", hram, edge_det=['clk_o'])
-
-
-class JTAGProvider(Elaboratable):
-    def __init__(self, cpu):
-        pass
-
-    def elaborate(self, platform):
-        return Module()  # JTAG is not connected anywhere
-
-
-class ClockResetProvider(Elaboratable):
-    def elaborate(self, platform):
-        m = Module()
-        m.d.comb += ClockSignal("sync").eq(platform.clk)
-        m.d.comb += ResetSignal("sync").eq(platform.rst)
-        return m
diff --git a/chipflow_lib/steps/silicon.py b/chipflow_lib/steps/silicon.py
index 1116ff8c..0ecbd187 100644
--- a/chipflow_lib/steps/silicon.py
+++ b/chipflow_lib/steps/silicon.py
@@ -1,32 +1,61 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
+import argparse
+import importlib.metadata
+import inspect
+import json
+import logging
 import os
+import requests
+import subprocess
 import sys
 import time
-import json
-import pprint
-import inspect
-import argparse
-import subprocess
-import importlib.metadata
 
-import requests
+import dotenv
+
+from amaranth import *
 
 from .. import ChipFlowError
-from ..platforms.silicon import SiliconPlatform
+from ..platforms import SiliconPlatform, top_interfaces
+
+
+logger = logging.getLogger(__name__)
+
+
+class SiliconTop(Elaboratable):
+    def __init__(self, config={}):
+        self._config = config
+
+    def elaborate(self, platform: SiliconPlatform):
+        m = Module()
+
+        platform.instantiate_ports(m)
+
+        # heartbeat led (to confirm clock/reset alive)
+        if ("config" in self._config["chipflow"]["silicon"] and
+           self._config["chipflow"]["silicon"]["debug"]["heartbeat"]):
+            heartbeat_ctr = Signal(23)
+            m.d.sync += heartbeat_ctr.eq(heartbeat_ctr + 1)
+            m.d.comb += platform.request("heartbeat").o.eq(heartbeat_ctr[-1])
+
+        top, interfaces = top_interfaces(self._config)
+        for n, t in top.items():
+            setattr(m.submodules, n, t)
+
+        return m
 
 
 class SiliconStep:
     """Prepare and submit the design for an ASIC."""
-
     def __init__(self, config):
-        self.project_id = config["chipflow"].get("project_id")
+        self.config = config
+        self.project_name = config["chipflow"].get("project_name")
         self.silicon_config = config["chipflow"]["silicon"]
-        self.platform = SiliconPlatform(pads=self.silicon_config["pads"])
+        self.platform = SiliconPlatform(config)
 
     def build_cli_parser(self, parser):
         action_argument = parser.add_subparsers(dest="action")
-        prepare_subparser = action_argument.add_parser(
+        action_argument.add_parser(
             "prepare", help=inspect.getdoc(self.prepare).splitlines()[0])
         submit_subparser = action_argument.add_parser(
             "submit", help=inspect.getdoc(self.submit).splitlines()[0])
@@ -36,7 +65,7 @@ def build_cli_parser(self, parser):
 
     def run_cli(self, args):
         if args.action == "submit" and not args.dry_run:
-            if self.project_id is None:
+            if self.project_name is None:
                 raise ChipFlowError(
                     "Key `chipflow.project_id` is not defined in chipflow.toml; "
                     "see https://chipflow.io/beta for details on how to join the beta")
@@ -55,11 +84,12 @@ def prepare(self):
 
         Returns the path to the RTLIL file.
         """
-        raise NotImplementedError
+        return self.platform.build(SiliconTop(self.config), name=self.config["chipflow"]["project_name"])
 
     def submit(self, rtlil_path, *, dry_run=False):
         """Submit the design to the ChipFlow cloud builder.
         """
+        dotenv.load_dotenv()
         git_head = subprocess.check_output(
             ["git", "-C", os.environ["CHIPFLOW_ROOT"],
              "rev-parse", "HEAD"],
@@ -69,8 +99,8 @@ def submit(self, rtlil_path, *, dry_run=False):
              "status", "--porcelain", "--untracked-files=no"]))
         submission_name = git_head
         if git_dirty:
+            logging.warning("Git tree is dirty, submitting anyway!")
             submission_name += f"-dirty.{time.strftime('%Y%m%d%M%H%S', time.gmtime())}"
-
         dep_versions = {
             "python": sys.version.split()[0]
         }
@@ -87,18 +117,27 @@ def submit(self, rtlil_path, *, dry_run=False):
             except importlib.metadata.PackageNotFoundError:
                 dep_versions[package] = None
         data = {
-            "projectId": self.project_id,
+            "projectId": self.project_name,
             "name": submission_name,
         }
+
+        pads = {}
+        for iface, port in self.platform._ports.items():
+            width = len(port.pins)
+            print(f"iface={iface}, port={port}, dir={port.direction}, width={width}")
+            if width > 1:
+                for i in range(width):
+                    padname = f"{iface}{i}"
+                    print(f"padname={padname}, port={port}, loc={port.pins[i:i+1]}, "
+                          f"dir={port.direction}, width={width}")
+                    pads[padname] = {'loc': port.pins[i:i+1], 'dir': port.direction}
+
         config = {
             "dependency_versions": dep_versions,
             "silicon": {
                 "process": self.silicon_config["process"],
-                "pad_ring": self.silicon_config["pad_ring"],
-                "pads": {
-                    pad_name: self.silicon_config["pads"][pad_name]
-                    for pad_name in self.platform._ports
-                },
+                "package": self.silicon_config["package"],
+                "pads": pads,
                 "power": self.silicon_config.get("power", {})
             }
         }
@@ -107,6 +146,8 @@ def submit(self, rtlil_path, *, dry_run=False):
             print(f"files['config']=\n{json.dumps(config, indent=2)}")
             return
 
+        logger.info(f"Submitting {submission_name} for project {self.project_name}")
+
         resp = requests.post(
             os.environ.get("CHIPFLOW_API_ENDPOINT", "https://app.chipflow-infra.com/api/builds"),
             auth=(os.environ["CHIPFLOW_API_KEY_ID"], os.environ["CHIPFLOW_API_KEY_SECRET"]),
@@ -135,3 +176,5 @@ def submit(self, rtlil_path, *, dry_run=False):
             else:
                 print(f"{resp_data['msg']} (#{resp_data['id']}: {resp_data['name']}); "
                       f"{resp_data['url']}")
+        else:
+            ChipFlowError(f"Unexpected response from API: {resp}")

From e415a2654820ae54ce14169f50560714164b03b6 Mon Sep 17 00:00:00 2001
From: Rob Taylor <rob.taylor@chipflow.io>
Date: Tue, 11 Feb 2025 16:30:04 +0000
Subject: [PATCH 3/6] tests: Update tests for pin-lock functionality

---
 tests/fixtures/chipflow-flexic.toml |  35 ----------
 tests/fixtures/mock.toml            |  25 +++++++
 tests/fixtures/mock_top.py          |  47 +++++++++++++
 tests/test_silicon_platform.py      |  15 ++--
 tests/test_silicon_step.py          |  21 +++---
 tests/test_utils.py                 | 105 ++++++++++++++++++++++++++++
 6 files changed, 199 insertions(+), 49 deletions(-)
 delete mode 100644 tests/fixtures/chipflow-flexic.toml
 create mode 100644 tests/fixtures/mock.toml
 create mode 100644 tests/fixtures/mock_top.py
 create mode 100644 tests/test_utils.py

diff --git a/tests/fixtures/chipflow-flexic.toml b/tests/fixtures/chipflow-flexic.toml
deleted file mode 100644
index 2a1bbaa5..00000000
--- a/tests/fixtures/chipflow-flexic.toml
+++ /dev/null
@@ -1,35 +0,0 @@
-[chipflow]
-project_id = 123
-
-[chipflow.steps]
-silicon = "thermostat.steps.silicon:MySiliconStep"
-
-[chipflow.silicon]
-process = "customer1"
-pad_ring = "cf20"
-
-[chipflow.silicon.pads]
-threshold_0 = { type = "i",   loc = "S1" }
-threshold_1 = { type = "i",   loc = "S2" }
-threshold_2 = { type = "i",   loc = "S3" }
-threshold_3 = { type = "i",   loc = "S4" }
-threshold_4 = { type = "i",   loc = "S5" }
-threshold_5 = { type = "i",   loc = "S6" }
-threshold_6 = { type = "i",   loc = "S7" }
-
-sclk        = { type = "o",   loc = "W3" }
-sdi         = { type = "i",   loc = "W2" }
-sdo         = { type = "o",   loc = "W1" }
-
-cool        = { type = "o",   loc = "E1" }
-heat        = { type = "o",   loc = "E3" }
-
-ssn         = { type = "o",   loc = "N2" }
-sys_clk     = { type = "clk", loc = "N3" }
-sys_rstn    = { type = "i",   loc = "N4" }
-
-[chipflow.silicon.power]
-vss         = { loc = "N1" }
-vssio       = { loc = "N5" }
-vddio       = { loc = "N6" }
-vdd         = { loc = "N7" }
diff --git a/tests/fixtures/mock.toml b/tests/fixtures/mock.toml
new file mode 100644
index 00000000..72e319e7
--- /dev/null
+++ b/tests/fixtures/mock.toml
@@ -0,0 +1,25 @@
+[chipflow]
+project_name = "proj-name"
+
+[chipflow.steps]
+silicon = "chipflow_lib.steps.silicon:SiliconStep"
+
+[chipflow.silicon]
+process = "ihp_sg13g2"
+package = "pga144"
+
+[chipflow.clocks]
+default = 'sys_clk'
+
+[chipflow.resets]
+default = 'sys_rst_n'
+
+[chipflow.silicon.pads]
+sys_clk     = { type = "clk", loc = "N3" }
+sys_rst_n    = { type = "i",   loc = "N4" }
+
+[chipflow.silicon.power]
+vss         = { loc = "N1" }
+vssio       = { loc = "N5" }
+vddio       = { loc = "N6" }
+vdd         = { loc = "N7" }
diff --git a/tests/fixtures/mock_top.py b/tests/fixtures/mock_top.py
new file mode 100644
index 00000000..185cae41
--- /dev/null
+++ b/tests/fixtures/mock_top.py
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: BSD-2-Clause
+from amaranth import Module
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
+
+from chipflow_lib.platforms import InputPinSignature, OutputPinSignature, BidirPinSignature
+
+__all__ = ["MockTop"]
+
+TestSignature1 = wiring.Signature({
+    "a": In(InputPinSignature(1)),
+    "b": In(InputPinSignature(5)),
+    "c": Out(OutputPinSignature(1)),
+    "d": Out(OutputPinSignature(10)),
+    "e": In(BidirPinSignature(1)),
+    "f": In(BidirPinSignature(7)),
+})
+
+TestSignature2 = wiring.Signature({
+    "a": Out(OutputPinSignature(1)),
+    "b": Out(OutputPinSignature(5)),
+    "c": In(InputPinSignature(1)),
+    "d": In(InputPinSignature(10)),
+    "e": Out(BidirPinSignature(1)),
+    "f": Out(BidirPinSignature(7)),
+})
+
+
+# ---------
+
+class MockTop(wiring.Component):
+    def __init__(self):
+        # Top level interfaces
+
+        interfaces = {
+            "test1" : Out(TestSignature1),
+            "test2": Out(TestSignature2)
+        }
+
+        super().__init__(interfaces)
+
+    def elaborate(self, platform):
+        m = Module()
+        for inpin, outpin in zip(self.test1.members, self.test2.members):
+            m.d.comb += inpin.eq(outpin)
+ 
+        return m
\ No newline at end of file
diff --git a/tests/test_silicon_platform.py b/tests/test_silicon_platform.py
index 495bbe2c..9795e0e0 100644
--- a/tests/test_silicon_platform.py
+++ b/tests/test_silicon_platform.py
@@ -2,10 +2,11 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 import os
-
 import unittest
+
+import tomli 
+
 from amaranth import *
-from amaranth.hdl import Fragment
 from amaranth.hdl._ir import Design
 
 from chipflow_lib import ChipFlowError
@@ -15,19 +16,23 @@
 class SiliconPlatformTestCase(unittest.TestCase):
     def setUp(self):
         os.environ["CHIPFLOW_ROOT"] = os.path.dirname(os.path.dirname(__file__))
+        current_dir = os.path.dirname(__file__)
+        customer_config = f"{current_dir}/fixtures/mock.toml"
+        with open(customer_config, "rb") as f:
+            self.config = tomli.load(f)
 
     def test_sync_domain_works(self):
         m = Module()
         m.domains += ClockDomain("sync")
 
-        fragment = SiliconPlatform(pads={})._prepare(m)
+        fragment = SiliconPlatform(self.config)._prepare(m)
         self.assertIsInstance(fragment, Design)
 
     def test_subfragment_works(self):
         m = Module()
         m.submodules += Module()
 
-        fragment = SiliconPlatform(pads={})._prepare(m)
+        fragment = SiliconPlatform(self.config)._prepare(m)
         self.assertIsInstance(fragment, Design)
 
     def test_wrong_clock_domain_name(self):
@@ -37,4 +42,4 @@ def test_wrong_clock_domain_name(self):
         with self.assertRaisesRegex(
                 ChipFlowError,
                 r"^Only a single clock domain, called 'sync', may be used$"):
-            SiliconPlatform(pads={}).build(m)
+            SiliconPlatform(self.config).build(m)
diff --git a/tests/test_silicon_step.py b/tests/test_silicon_step.py
index ef8fce24..0df19433 100644
--- a/tests/test_silicon_step.py
+++ b/tests/test_silicon_step.py
@@ -1,11 +1,11 @@
 # SPDX-License-Identifier: BSD-2-Clause
-
 import io
 import json
 import os
 import tomli
 import unittest
 from contextlib import redirect_stdout
+from pprint import pformat
 from unittest.mock import patch
 
 from chipflow_lib.steps.silicon import SiliconStep
@@ -29,7 +29,7 @@ def json(self):
             "msg": "msg",
             "url": "https://example.com/build-url/",
             "name": "name",
-            "id": 123,
+            "id": "proj-name",
         }, 200)
 
     return MockResponse(None, 404)
@@ -41,9 +41,10 @@ def setUp(self):
         os.environ["CHIPFLOW_API_KEY_ID"] = "keyid"
         os.environ["CHIPFLOW_API_KEY_SECRET"] = "keysecret"
 
+    @patch('dotenv.load_dotenv')
     @patch('requests.post', side_effect=mocked_requests_post)
-    def test_submit_happy_path(self, mock_requests_post):
-        customer_config = f"{current_dir}/fixtures/chipflow-flexic.toml"
+    def test_submit_happy_path(self, mock_requests_post, mock_dotenv):
+        customer_config = f"{current_dir}/fixtures/mock.toml"
         with open(customer_config, "rb") as f:
             config_dict = tomli.load(f)
 
@@ -53,7 +54,7 @@ def test_submit_happy_path(self, mock_requests_post):
         with redirect_stdout(f):
             silicon_step.submit(current_dir + "/fixtures/mock.rtlil")
         output = f.getvalue()
-        assert 'msg (#123: name); https://example.com/build-url/' in output, "The printed output is correct."
+        assert 'msg (#proj-name: name); https://example.com/build-url/' in output, "The printed output is correct."
 
         args = mock_requests_post.call_args_list[0][0]
         kwargs = mock_requests_post.call_args_list[0][1]
@@ -63,7 +64,7 @@ def test_submit_happy_path(self, mock_requests_post):
         rtlil = files["rtlil"].read()
         assert args[0] == 'https://app.chipflow-infra.com/api/builds'
         assert kwargs["auth"] == ("keyid", "keysecret")
-        assert data["projectId"] == 123
+        assert data["projectId"] == 'proj-name'
         assert isinstance(data["name"], str), "Name is a string"
         assert list(config["dependency_versions"]) == [
             "python",
@@ -73,10 +74,10 @@ def test_submit_happy_path(self, mock_requests_post):
             "amaranth-orchard", "amaranth-vexriscv",
         ], "We have entries for the the dependency versions"
 
+        print(pformat(config))
         assert config["silicon"] == {
-            'process': 'customer1',
-            'pad_ring':
-            'cf20',
+            'process': 'ihp_sg13g2',
+            'package': 'pga144',
             'pads': {},
             'power': {
                 'vss': {'loc': 'N1'},
@@ -86,3 +87,5 @@ def test_submit_happy_path(self, mock_requests_post):
             }
         }
         assert rtlil == b"fake-rtlil", "The RTL file was passed through."
+
+        assert mock_dotenv.called
diff --git a/tests/test_utils.py b/tests/test_utils.py
new file mode 100644
index 00000000..e0f77280
--- /dev/null
+++ b/tests/test_utils.py
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: BSD-2-Clause
+import itertools
+import logging
+import pytest #noqa 
+
+from pprint import pformat
+
+from amaranth.lib import io
+
+from chipflow_lib.platforms.utils import PinSignature, OutputPinSignature, InputPinSignature, BidirPinSignature, _PinAnnotation, _PinAnnotationModel
+from chipflow_lib.platforms.utils import PinList, _group_consecutive_items,_find_contiguous_sequence, _Side
+
+
+logger = logging.getLogger(__name__)
+
+
+def gen_quad_pins(width, height) -> PinList:
+    return sorted(
+            [e for e in itertools.product((_Side.N, _Side.S), range(width))] +
+            [e for e in itertools.product((_Side.W, _Side.E), range(height))]
+           )
+
+
+def test_group_consecutive_items_null():
+    ordering = gen_quad_pins(50,60)
+    pins = ordering.copy()
+    groups = _group_consecutive_items(pins,pins)
+    assert len(groups.keys()) == 1
+    assert len(ordering) in groups.keys()
+
+def test_group_consecutive_items_nonconsecutive():
+    ordering = gen_quad_pins(50,60)
+    pins = ordering[0:6] + ordering[7:70] + ordering[71:180] + ordering[181:]
+    logger.debug(f"{ordering} {pins}")
+    groups = _group_consecutive_items(ordering,pins)
+    logger.debug(f"\n{pformat(groups)}")
+    assert len(ordering) == 50*2 + 60*2
+    assert len(groups.keys()) == 4
+    assert sum(groups.keys()) == len(ordering) - 3
+    assert 6 in groups.keys()
+    assert 70 - 7 in groups.keys()
+    assert 180 - 71 in groups.keys()
+    assert len(ordering) -181 in groups.keys()
+
+def test_find_contiguous_sequence():
+    ordering = gen_quad_pins(50,60)
+    pins = ordering[0:6] + ordering[7:70] + ordering[71:180] + ordering[181:]
+    seq = _find_contiguous_sequence(ordering, pins, 120)
+    logger.debug(f"\n{pformat(seq)}")
+    logger.debug(f"{ordering[71:180] + ordering[181:191]}")
+    assert len(seq) == 120
+    assert seq == ordering[71:180] + ordering[181:192]
+
+
+def test_pin_signature():
+    sig_bidir = PinSignature(io.Direction.Bidir, width=8)
+    assert isinstance(sig_bidir, PinSignature)
+    assert sig_bidir._direction == io.Direction.Bidir
+    assert sig_bidir._width == 8
+    assert "o" in sig_bidir.members
+    assert "oe" in sig_bidir.members
+    assert "i" in sig_bidir.members
+
+    sig_output = OutputPinSignature(width=4)
+    assert isinstance(sig_output, PinSignature)
+    assert sig_output._direction == io.Direction.Output
+    assert sig_output._width == 4
+    assert "o" in sig_output.members
+    assert "oe" not in sig_output.members
+    assert "i" not in sig_output.members
+
+    sig_input = InputPinSignature(width=2)
+    assert isinstance(sig_input, PinSignature)
+    assert sig_input._direction == io.Direction.Input
+    assert sig_input._width == 2
+    assert "o" not in sig_input.members
+    assert "oe" not in sig_output.members
+    assert "i" in sig_input.members
+
+    sig_bidir_fn = BidirPinSignature(width=1)
+    assert isinstance(sig_bidir_fn, PinSignature)
+    assert sig_bidir_fn._direction == io.Direction.Bidir
+    assert sig_bidir_fn._width == 1
+    assert "o" in sig_bidir_fn.members
+    assert "oe" in sig_bidir_fn.members
+    assert "i" in sig_bidir_fn.members
+
+def test_pin_annotation_model():
+    model = _PinAnnotationModel(direction=io.Direction.Output, width=32)
+    assert model.direction == "o"
+    assert model.width == 32
+
+def test_pin_annotation():
+    annotation = _PinAnnotation(direction=io.Direction.Input, width=16)
+    assert isinstance(annotation, _PinAnnotation)
+    assert annotation.model.direction == "i"
+    assert annotation.model.width == 16
+
+def test_pin_annotation_as_json():
+    annotation = _PinAnnotation(direction=io.Direction.Bidir, width=8)
+    json_output = annotation.as_json()
+    print(f"json_output: {json_output}") # Debug print using print()
+    assert isinstance(json_output, dict)
+    assert json_output["direction"] == "io"
+    assert json_output["width"] == 8
\ No newline at end of file

From 3a84216ba88f3186637baba6ad87d6846bff3466 Mon Sep 17 00:00:00 2001
From: Rob Taylor <rob.taylor@chipflow.io>
Date: Tue, 11 Feb 2025 16:33:13 +0000
Subject: [PATCH 4/6] Update pyproject.toml and add pdm.lock

---
 .github/workflows/main.yaml |    1 -
 .gitignore                  |    2 +-
 pdm.lock                    | 1397 +++++++++++++++++++++++++++++++++++
 pyproject.toml              |   51 +-
 4 files changed, 1433 insertions(+), 18 deletions(-)
 create mode 100644 pdm.lock

diff --git a/.github/workflows/main.yaml b/.github/workflows/main.yaml
index 3932ee8e..c7980699 100644
--- a/.github/workflows/main.yaml
+++ b/.github/workflows/main.yaml
@@ -19,7 +19,6 @@ jobs:
         uses: pdm-project/setup-pdm@v4
       - name: Install dependencies
         run: |
-          pdm lock --dev
           pdm install
       - name: Run tests
         run: |
diff --git a/.gitignore b/.gitignore
index d7b78032..584bee2d 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,13 +2,13 @@
 __pycache__/
 *.egg-info
 /dist
+/log*
 
 # pdm
 /.pdm-plugins
 /.pdm-python
 /.pdm-build
 /.venv
-/pdm.lock
 
 # pytest
 /.pytest_cache
diff --git a/pdm.lock b/pdm.lock
new file mode 100644
index 00000000..80606cf1
--- /dev/null
+++ b/pdm.lock
@@ -0,0 +1,1397 @@
+# This file is @generated by PDM.
+# It is not intended for manual editing.
+
+[metadata]
+groups = ["default", "lint", "test"]
+strategy = ["inherit_metadata"]
+lock_version = "4.5.0"
+content_hash = "sha256:c101435debd2c023d993687fb5bf233f633eecf35b47e75dc57b0e4dc6c38a12"
+
+[[metadata.targets]]
+requires_python = "~=3.10"
+
+[[package]]
+name = "accessible-pygments"
+version = "0.0.5"
+requires_python = ">=3.9"
+summary = "A collection of accessible pygments styles"
+groups = ["default"]
+dependencies = [
+    "pygments>=1.5",
+]
+files = [
+    {file = "accessible_pygments-0.0.5-py3-none-any.whl", hash = "sha256:88ae3211e68a1d0b011504b2ffc1691feafce124b845bd072ab6f9f66f34d4b7"},
+    {file = "accessible_pygments-0.0.5.tar.gz", hash = "sha256:40918d3e6a2b619ad424cb91e556bd3bd8865443d9f22f1dcdf79e33c8046872"},
+]
+
+[[package]]
+name = "alabaster"
+version = "0.7.16"
+requires_python = ">=3.9"
+summary = "A light, configurable Sphinx theme"
+groups = ["default", "test"]
+files = [
+    {file = "alabaster-0.7.16-py3-none-any.whl", hash = "sha256:b46733c07dce03ae4e150330b975c75737fa60f0a7c591b6c8bf4928a28e2c92"},
+    {file = "alabaster-0.7.16.tar.gz", hash = "sha256:75a8b99c28a5dad50dd7f8ccdd447a121ddb3892da9e53d1ca5cca3106d58d65"},
+]
+
+[[package]]
+name = "amaranth"
+version = "0.5.4"
+requires_python = "~=3.8"
+summary = "Amaranth hardware definition language"
+groups = ["default"]
+dependencies = [
+    "Jinja2~=3.0",
+    "importlib-resources; python_version < \"3.9\"",
+    "jschon~=0.11.1",
+    "pyvcd<0.5,>=0.2.2",
+]
+files = [
+    {file = "amaranth-0.5.4-py3-none-any.whl", hash = "sha256:ce7473b4220acc78474474fd132177ca545fb144d4e69e1c7dbfc2ed7d32bcf3"},
+    {file = "amaranth-0.5.4.tar.gz", hash = "sha256:a0ea7ffe358ab00d5524b53c43277d279723437be146c8250e26f6b349b8a4fd"},
+]
+
+[[package]]
+name = "amaranth-boards"
+version = "0.1.dev253"
+requires_python = "~=3.9"
+git = "https://github.com/amaranth-lang/amaranth-boards"
+revision = "9d97c4816288c9c2cc304d9280c2c63178d50d2f"
+summary = "Board and connector definitions for Amaranth HDL"
+groups = ["default"]
+dependencies = [
+    "amaranth<0.7,>=0.5",
+]
+
+[[package]]
+name = "amaranth-soc"
+version = "0.1a1.dev24"
+requires_python = "~=3.9"
+git = "https://github.com/amaranth-lang/amaranth-soc"
+revision = "5c43cf58f15d9cd9c69ff83c97997708d386b2dc"
+summary = "System on Chip toolkit for Amaranth HDL"
+groups = ["default"]
+dependencies = [
+    "amaranth<0.6,>=0.5",
+]
+
+[[package]]
+name = "annotated-types"
+version = "0.7.0"
+requires_python = ">=3.8"
+summary = "Reusable constraint types to use with typing.Annotated"
+groups = ["default"]
+dependencies = [
+    "typing-extensions>=4.0.0; python_version < \"3.9\"",
+]
+files = [
+    {file = "annotated_types-0.7.0-py3-none-any.whl", hash = "sha256:1f02e8b43a8fbbc3f3e0d4f0f4bfc8131bcb4eebe8849b8e5c773f3a1c582a53"},
+    {file = "annotated_types-0.7.0.tar.gz", hash = "sha256:aff07c09a53a08bc8cfccb9c85b05f1aa9a2a6f23728d790723543408344ce89"},
+]
+
+[[package]]
+name = "astroid"
+version = "3.3.8"
+requires_python = ">=3.9.0"
+summary = "An abstract syntax tree for Python with inference support."
+groups = ["default"]
+dependencies = [
+    "typing-extensions>=4.0.0; python_version < \"3.11\"",
+]
+files = [
+    {file = "astroid-3.3.8-py3-none-any.whl", hash = "sha256:187ccc0c248bfbba564826c26f070494f7bc964fd286b6d9fff4420e55de828c"},
+    {file = "astroid-3.3.8.tar.gz", hash = "sha256:a88c7994f914a4ea8572fac479459f4955eeccc877be3f2d959a33273b0cf40b"},
+]
+
+[[package]]
+name = "attrs"
+version = "24.2.0"
+requires_python = ">=3.7"
+summary = "Classes Without Boilerplate"
+groups = ["default"]
+dependencies = [
+    "importlib-metadata; python_version < \"3.8\"",
+]
+files = [
+    {file = "attrs-24.2.0-py3-none-any.whl", hash = "sha256:81921eb96de3191c8258c199618104dd27ac608d9366f5e35d011eae1867ede2"},
+    {file = "attrs-24.2.0.tar.gz", hash = "sha256:5cfb1b9148b5b086569baec03f20d7b6bf3bcacc9a42bebf87ffaaca362f6346"},
+]
+
+[[package]]
+name = "babel"
+version = "2.17.0"
+requires_python = ">=3.8"
+summary = "Internationalization utilities"
+groups = ["default", "test"]
+dependencies = [
+    "pytz>=2015.7; python_version < \"3.9\"",
+]
+files = [
+    {file = "babel-2.17.0-py3-none-any.whl", hash = "sha256:4d0b53093fdfb4b21c92b5213dba5a1b23885afa8383709427046b21c366e5f2"},
+    {file = "babel-2.17.0.tar.gz", hash = "sha256:0c54cffb19f690cdcc52a3b50bcbf71e07a808d1c80d549f2459b9d2cf0afb9d"},
+]
+
+[[package]]
+name = "beautifulsoup4"
+version = "4.13.3"
+requires_python = ">=3.7.0"
+summary = "Screen-scraping library"
+groups = ["default"]
+dependencies = [
+    "soupsieve>1.2",
+    "typing-extensions>=4.0.0",
+]
+files = [
+    {file = "beautifulsoup4-4.13.3-py3-none-any.whl", hash = "sha256:99045d7d3f08f91f0d656bc9b7efbae189426cd913d830294a15eefa0ea4df16"},
+    {file = "beautifulsoup4-4.13.3.tar.gz", hash = "sha256:1bd32405dacc920b42b83ba01644747ed77456a65760e285fbc47633ceddaf8b"},
+]
+
+[[package]]
+name = "certifi"
+version = "2024.8.30"
+requires_python = ">=3.6"
+summary = "Python package for providing Mozilla's CA Bundle."
+groups = ["default", "test"]
+files = [
+    {file = "certifi-2024.8.30-py3-none-any.whl", hash = "sha256:922820b53db7a7257ffbda3f597266d435245903d80737e34f8a45ff3e3230d8"},
+    {file = "certifi-2024.8.30.tar.gz", hash = "sha256:bec941d2aa8195e248a60b31ff9f0558284cf01a52591ceda73ea9afffd69fd9"},
+]
+
+[[package]]
+name = "charset-normalizer"
+version = "3.4.0"
+requires_python = ">=3.7.0"
+summary = "The Real First Universal Charset Detector. Open, modern and actively maintained alternative to Chardet."
+groups = ["default", "test"]
+files = [
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+name = "wasmtime"
+version = "25.0.0"
+requires_python = ">=3.8"
+summary = "A WebAssembly runtime powered by Wasmtime"
+groups = ["default"]
+dependencies = [
+    "importlib-resources>=5.10",
+]
+files = [
+    {file = "wasmtime-25.0.0-py3-none-any.whl", hash = "sha256:22aa59fc6e01deec8a6703046f82466090d5811096a3bb5c169907e36c842af1"},
+    {file = "wasmtime-25.0.0-py3-none-macosx_10_13_x86_64.whl", hash = "sha256:13e9a718e9d580c1738782cc19f4dcb9fb068f7e51778ea621fd664f4433525b"},
+    {file = "wasmtime-25.0.0-py3-none-macosx_11_0_arm64.whl", hash = "sha256:5bdf1214ee3ee78a4a8a92da339f4c4c8c109e65af881b37f4adfc05d02af426"},
+    {file = "wasmtime-25.0.0-py3-none-manylinux1_x86_64.whl", hash = "sha256:b4364e14d44e3b7afe6a40bf608e9d0d2c40b09dece441d20f4f6e31906b729c"},
+    {file = "wasmtime-25.0.0-py3-none-manylinux2014_aarch64.whl", hash = "sha256:a07445073cf36a6e5d1dc28246a897dcbdaa537ba8be8805be65422ecca297eb"},
+    {file = "wasmtime-25.0.0-py3-none-musllinux_1_2_x86_64.whl", hash = "sha256:53d5f614348a28aabdf80ae4f6fdfa803031af1f74ada03826fd4fd43aeee6c8"},
+    {file = "wasmtime-25.0.0-py3-none-win_amd64.whl", hash = "sha256:f8a2a213b9179965db2d2eedececd69a37e287e902330509afae51c71a3a6842"},
+]
+
+[[package]]
+name = "yowasp-nextpnr-ecp5"
+version = "0.7.0.11.post528.dev0"
+summary = "nextpnr-ecp5 FPGA place and route tool"
+groups = ["default"]
+dependencies = [
+    "yowasp-runtime~=1.1",
+]
+files = [
+    {file = "yowasp_nextpnr_ecp5-0.7.0.11.post528.dev0-py3-none-any.whl", hash = "sha256:102d3e81004c402e4422121197fa4eaf5090bd2d6d7e483312f2191233165e66"},
+]
+
+[[package]]
+name = "yowasp-runtime"
+version = "1.68"
+requires_python = "~=3.8"
+summary = "Common runtime for YoWASP packages"
+groups = ["default"]
+dependencies = [
+    "importlib-resources; python_version < \"3.9\"",
+    "platformdirs<5,>=3.0",
+    "wasmtime<29,>=21.0.0",
+]
+files = [
+    {file = "yowasp_runtime-1.68-py3-none-any.whl", hash = "sha256:e6a5029dd6bc8608cb6715404a58e212d42046e4e0056da0a56667c1381e028f"},
+]
+
+[[package]]
+name = "yowasp-yosys"
+version = "0.48.0.0.post834"
+summary = "Yosys Open SYnthesis Suite"
+groups = ["default"]
+dependencies = [
+    "click",
+    "importlib-resources; python_version < \"3.9\"",
+    "yowasp-runtime~=1.12",
+]
+files = [
+    {file = "yowasp_yosys-0.48.0.0.post834-py3-none-any.whl", hash = "sha256:6a53cdb48083c7ac88dc9e5312e72e92f5afd69aeea412274505c82f8d8d374c"},
+]
+
+[[package]]
+name = "zipp"
+version = "3.21.0"
+requires_python = ">=3.9"
+summary = "Backport of pathlib-compatible object wrapper for zip files"
+groups = ["default"]
+files = [
+    {file = "zipp-3.21.0-py3-none-any.whl", hash = "sha256:ac1bbe05fd2991f160ebce24ffbac5f6d11d83dc90891255885223d42b3cd931"},
+    {file = "zipp-3.21.0.tar.gz", hash = "sha256:2c9958f6430a2040341a52eb608ed6dd93ef4392e02ffe219417c1b28b5dd1f4"},
+]
diff --git a/pyproject.toml b/pyproject.toml
index d17d51c0..8a82f5ab 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -2,9 +2,6 @@
 
 # Project metadata
 
-[tool.pdm.version]
-source = "scm"
-
 [project]
 name = "chipflow-lib"
 dynamic = ["version"]
@@ -16,13 +13,11 @@ authors = [
 ]
 license = {file = "LICENSE.md"}
 
-requires-python = ">=3.9"
+requires-python = ">=3.10"
 dependencies = [
     "amaranth>=0.5,<0.7",
     "amaranth-soc @ git+https://github.com/amaranth-lang/amaranth-soc",
     "amaranth-boards @ git+https://github.com/amaranth-lang/amaranth-boards",
-    "amaranth-stdio @ git+https://github.com/amaranth-lang/amaranth-stdio",
-    "amaranth-orchard @ git+https://github.com/ChipFlow/amaranth-orchard",
     "yowasp-yosys>=0.41.0.0",
     "yowasp-nextpnr-ecp5>=0.7",
     "yowasp-runtime",
@@ -30,6 +25,10 @@ dependencies = [
     "jsonschema>=4.17.3",
     "doit>=0.36.0",
     "requests>=2.30.0",
+    "python-dotenv>=1.0.1",
+    "pydantic>=2.10.6",
+    "sphinx-book-theme>=1.1.3",
+    "sphinx-autoapi>=3.5.0",
 ]
 
 [project.scripts]
@@ -43,17 +42,37 @@ build-backend = "pdm.backend"
 
 # Development workflow configuration
 
-[tool.pdm.dev-dependencies]
-test = [
-    "pytest>=7.2.0",
-    "sphinx>=7.1.2",
-]
-lint = [
-    "pycodestyle>=2.11",
-]
+[tool.pyright]
+diagnosticMode=false
+typeCheckingMode = "off"
+reportInvalidTypeForm = false
+reportMissingImports = false
+reportUnboundVariable = false
+
+[tool.ruff]
+include = ["pyproject.toml", "**/*.py", "chipflow.toml"]
+
+[tool.ruff.lint]
+ignore = ['F403', 'F405']
+
+[tool.pdm.version]
+source = "scm"
 
 [tool.pdm.scripts]
+test-cov.cmd = "pytest --cov=chipflow_lib --cov-report=html"
 test.cmd = "pytest"
 test-docs.cmd = "sphinx-build -b doctest docs/ docs/_build"
-lint.cmd = "pycodestyle --config=./.pycodestyle chipflow_lib"
-document.cmd = "sphinx-build docs/ docs/_build/ -W --keep-going"
+lint.cmd = "ruff check"
+docs.cmd = "sphinx-build docs/ docs/_build/ -W --keep-going"
+
+
+[dependency-groups]
+lint = [
+    "ruff",
+    "pytest-cov",
+]
+test = [
+    "pytest>=7.2.0",
+    "sphinx>=7.1.2",
+    "pytest-cov>=6.0.0",
+]

From 9b913ab83d435a509d0eb2109578547da6710017 Mon Sep 17 00:00:00 2001
From: Rob Taylor <rob.taylor@chipflow.io>
Date: Tue, 11 Feb 2025 16:34:28 +0000
Subject: [PATCH 5/6] docs: update for pin-lock and tweak CI for docs

---
 .github/workflows/deploy-docs.yml  |  30 +++++++++++
 .github/workflows/main.yaml        |  45 -----------------
 .github/workflows/preview-docs.yml |  36 +++++++++++++
 docs/_static/chipflow-logo.png     | Bin 0 -> 92159 bytes
 docs/_static/chipflow-logo.svg     |  18 +++++++
 docs/chipflow-toml-guide.rst       |  70 ++++++++++++++++++--------
 docs/conf.py                       |  78 ++++++++++++++++++++++++++---
 docs/example-chipflow.toml         |  67 +++++++++++++------------
 docs/index.rst                     |  15 ++++--
 9 files changed, 251 insertions(+), 108 deletions(-)
 create mode 100644 .github/workflows/deploy-docs.yml
 create mode 100644 .github/workflows/preview-docs.yml
 create mode 100644 docs/_static/chipflow-logo.png
 create mode 100644 docs/_static/chipflow-logo.svg

diff --git a/.github/workflows/deploy-docs.yml b/.github/workflows/deploy-docs.yml
new file mode 100644
index 00000000..c19b712f
--- /dev/null
+++ b/.github/workflows/deploy-docs.yml
@@ -0,0 +1,30 @@
+# .github/workflows/deploy.yml
+name: Deploy
+on:
+  push:
+    branches:
+      - main
+jobs:
+  deploy:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+
+      - name: Setup PDM
+        uses: pdm-project/setup-pdm@v4
+        with:
+          python-version: 3.12
+          cache: true
+
+      - name: Install dependencies
+        run: pdm install
+
+      - name: Build docs
+        run: pdm docs
+
+      - uses: JamesIves/github-pages-deploy-action@v4
+        with:
+          folder: docs/_build
+          branch: gh-pages
+          clean-exclude: pr-preview
+          force: false
diff --git a/.github/workflows/main.yaml b/.github/workflows/main.yaml
index c7980699..42792e40 100644
--- a/.github/workflows/main.yaml
+++ b/.github/workflows/main.yaml
@@ -39,48 +39,3 @@ jobs:
       - name: Check source code licenses
         run: |
           docker run --platform=linux/amd64 -v ${PWD}:/src ghcr.io/google/addlicense -v -check -l BSD-2-Clause -c "ChipFlow" -s=only -ignore **/__init__.py **/*.py
-
-  build-docs:
-    needs: test
-    runs-on: ubuntu-22.04
-    steps:
-      - name: Checkout
-        uses: actions/checkout@v4
-      - name: Set up PDM
-        uses: pdm-project/setup-pdm@v4
-        with:
-          python-version: 3.9
-      - name: Install deps
-        run: pdm install
-      - name: Build docs
-        run: pdm run document
-      - name: Upload docs artifact
-        uses: actions/upload-artifact@v4
-        with:
-          name: docs
-          path: docs/_build
-
-  publish-docs:
-    needs: build-docs
-    if: ${{ github.repository == 'chipflow/chipflow-lib' }}
-    runs-on: ubuntu-latest
-    steps:
-      - name: Checkout
-        uses: actions/checkout@v4
-        with:
-          fetch-depth: 0
-      - name: Download docs artifact
-        uses: actions/download-artifact@v4
-        with:
-          name: docs
-          path: docs/
-      - name: Publish "latest" docs
-        if: ${{ github.event_name == 'push' && github.event.ref == 'refs/heads/main' }}
-        uses: JamesIves/github-pages-deploy-action@releases/v4
-        with:
-          repository-name: chipflow/chipflow.github.io
-          ssh-key: ${{ secrets.PAGES_DEPLOY_KEY }}
-          branch: main
-          folder: docs/
-          target-folder: chipflow-lib/latest/
-        
\ No newline at end of file
diff --git a/.github/workflows/preview-docs.yml b/.github/workflows/preview-docs.yml
new file mode 100644
index 00000000..81dbb37f
--- /dev/null
+++ b/.github/workflows/preview-docs.yml
@@ -0,0 +1,36 @@
+# .github/workflows/preview.yml
+name: Deploy PR previews
+concurrency: preview-${{ github.ref }}
+on:
+  pull_request:
+    types:
+      - opened
+      - reopened
+      - synchronize
+      - closed
+jobs:
+  deploy-preview:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+
+      - name: Setup PDM
+        uses: pdm-project/setup-pdm@v4
+        with:
+          python-version: 3.12
+          cache: true
+
+      - name: Install dependencies
+        run: pdm install
+
+      - name: Build docs
+        run: pdm docs
+        if: github.event.action != 'closed'
+
+      - uses: rossjrw/pr-preview-action@v1
+        with:
+          source-dir: docs/_build
+          preview-branch: gh-pages
+          umbrella-dir: pr-preview
+          action: auto
+          pages-base-url: chipflow-lib.docs.chipflow-infra.com
diff --git a/docs/_static/chipflow-logo.png b/docs/_static/chipflow-logo.png
new file mode 100644
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diff --git a/docs/chipflow-toml-guide.rst b/docs/chipflow-toml-guide.rst
index 0990e83e..07d7cbc0 100644
--- a/docs/chipflow-toml-guide.rst
+++ b/docs/chipflow-toml-guide.rst
@@ -1,5 +1,5 @@
-Intro to chipflow.toml
-======================
+Intro to ``chipflow.toml``
+==========================
 
 The ``chipflow.toml`` file provides configuration for your design with the ChipFlow platform.
 
@@ -14,25 +14,55 @@ Let's start with a typical example:
    # Assert that example-chipflow.toml matches the current config schema. If 
    # this test fails, then its likely that the content in this file will need
    # to be updated.
-   from chipflow_lib.cli import _parse_config_file
+   from chipflow_lib import _parse_config_file
    _parse_config_file("docs/example-chipflow.toml")
 
-project_id
-===========
+``[chipflow]``
+--------------
 
-The ``project_id`` is set to the project ID which you can get from the ChipFlow app project page.
+.. code-block:: TOML
+
+   [chipflow]
+   project_name = "my_project"
+
+
+The ``project_name`` is a human-readable identifier for this project. If not set, the tool and library will use the project name configured in ``pyproject.toml``.
+
+``[chipflow.steps]``
+--------------------
+
+The ``steps`` section allows overriding or addition to the standard steps available from `chipflow_lib`_.
+
+For example, if you want to override the standard silicon preparation step, you could derive from :class:`chipflow_lib.steps.silicon.SiliconStep`, add your custom functionality
+and add the following to your `chipflow.toml`, with the appropriate Python `qualified name`_ :
+
+.. code-block:: TOML
+
+   [chipflow.stepe]
+   silicon = "my_design.steps.silicon:SiliconStep"
 
-steps
-=====
 
-The ``steps`` define the Python class which will be used as an entry point to these parts of the ChipFlow process.
 You probably won't need to change these if you're starting from an example repository.
 
-silicon
-=======
+.. _chipflow_lib: https://github.com/ChipFlow/chipflow-lib]
+.. _qualified name: https://docs.python.org/3/glossary.html#term-qualified-name
 
-The ``silicon`` section sets the Foundry ``process`` we are targeting for manufacturing, and the physical ``pad_ring`` we want to place our design inside.
-You'll choose the ``process`` and ``pad_ring`` based in the requirements of your design. 
+
+``[chipflow.clocks]``
+---------------------
+
+``[chipflow.silicon]``
+----------------------
+
+.. code-block:: TOML
+
+   [chipflow.silicon]
+   process = "ihp_sg13g2"
+   package = "pga144"
+
+
+The ``silicon`` section sets the Foundry ``process`` we are targeting for manufacturing, and the physical ``package`` we want to place our design inside.
+You'll choose the ``process`` and ``package`` based in the requirements of your design. 
 
 Available processes
 -------------------
@@ -56,12 +86,8 @@ Available pad rings
 +----------+-----------+--------------------+------------------------------------+
 | Pad ring | Pad count | Pad locations      | Notes                              |
 +==========+===========+====================+====================================+
-|| caravel || TBC      || TBC               || The `Caravel Harness`_ contains   |
-||         ||          ||                   || additional logic which wraps your |
-||         ||          ||                   || design.                           |
-||         ||          ||                   || It handles its own power pins.    |
 +----------+-----------+--------------------+------------------------------------+
-|| cf20    || 20       || ``N1`` ... ``N7`` ||                                   |
+|| cf20    || 20       || ``N1`` ... ``N7`` ||   Bare die package with 20 pins   |
 ||         ||          || ``S1`` ... ``S7`` ||                                   |
 ||         ||          || ``E1`` ... ``E3`` ||                                   |
 ||         ||          || ``W1`` ... ``W3`` ||                                   |
@@ -74,10 +100,12 @@ Available pad rings
 +----------+-----------+--------------------+------------------------------------+
 
 
+
+
 silicon.pads
 ============
 
-The ``silicon.pads`` section lists the pads we will be using. 
+The ``silicon.pads`` section lists special pads. In general you are unlikely to need to add to this. 
 
 For each pad, there's a label which is used by our design, and what ``type`` and ``loc`` each pad should be.
 
@@ -86,8 +114,8 @@ type
 
 The ``type`` for each pad can be set to one of:
 
-clk
-   External clock.
+clock
+   External clock input.
 
 i
    Input.
diff --git a/docs/conf.py b/docs/conf.py
index 5950dec3..14e581d2 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -4,16 +4,23 @@
 # Add parent folder to path so we can pick up module
 import os
 import sys
+sys.path.insert(0, os.path.abspath('../../chipflow_lib'))
+
+from chipflow_lib import __version__
+
 doctest_path = [os.path.abspath('..')]
 
 # -- Project information
 
-project = 'ChipFlow'
-copyright = 'ChipFlow'
-author = 'ChipFlow'
+project = 'chipflow-lib'
+copyright = 'ChipFlow Limited, 2021-2025'
+author = 'ChipFlow Platform Team'
 
 release = 'alpha'
-version = '0.1.0'
+version = __version__
+
+master_doc = "index"
+
 
 # -- General configuration
 
@@ -21,15 +28,72 @@
     'sphinx.ext.duration',
     'sphinx.ext.doctest',
     'sphinx.ext.autodoc',
-    'sphinx.ext.autosummary',
     'sphinx.ext.intersphinx',
+    'autoapi.extension',
+    'sphinx.ext.napoleon'
+]
+
+html_theme = 'sphinx_book_theme'
+html_logo = '_static/chipflow-logo.svg'
+html_title = "ChipFlow Platform Documentation"
+
+
+html_sidebars = {
+    '**': [
+        'relations.html',  # needs 'show_related': True theme option to display
+        'searchbox.html',
+    ]
+}
+
+html_static_path = ['_static']
+
+html_theme_options = {
+    "home_page_in_toc": True,
+    "repository_url": "https://github.com/ChipFlow/chipflow-lib",
+    "repository_branch": "master",
+    "path_to_docs": "docs",
+    "use_repository_button": True,
+    "use_edit_page_button": True,
+    "use_issues_button": True,
+    "show_navbar_depth": 3,
+    # "announcement": "<b>v3.0.0</b> is now out! See the Changelog for details",
+}
+
+autodoc_typehints = 'description'
+
+autoapi_dirs = ["../chipflow_lib"]
+autoapi_options = [
+    'members',
+    'undoc-members',
+    'show-inheritance',
+    'show-module-summary',
+    'imported-members',
 ]
 
 intersphinx_mapping = {
-    'python': ('https://docs.python.org/3/', None),
-    'sphinx': ('https://www.sphinx-doc.org/en/master/', None),
+    'py': ('https://docs.python.org/3/', None),
+    'amaranth': ('https://amaranth-lang.org/docs/amaranth/v0.5.4/', None),
+    # 'chipflow': ('https://docs.chipflow.io/', None),
 }
 intersphinx_disabled_domains = ['std']
 
+# Napoleon settings
+napoleon_google_docstring = True
+napoleon_numpy_docstring = True
+napoleon_include_init_with_doc = True
+napoleon_include_private_with_doc = True
+napoleon_include_special_with_doc = True
+napoleon_use_admonition_for_examples = False
+napoleon_use_admonition_for_notes = False
+napoleon_use_admonition_for_references = False
+napoleon_use_ivar = False
+napoleon_use_param = True
+napoleon_use_rtype = True
+
+rst_prolog = """
+.. role:: py(code)
+   :language: python
+"""
+
 # -- Options for EPUB output
 epub_show_urls = 'footnote'
diff --git a/docs/example-chipflow.toml b/docs/example-chipflow.toml
index 5db4cfa0..3c7c31a5 100644
--- a/docs/example-chipflow.toml
+++ b/docs/example-chipflow.toml
@@ -1,38 +1,43 @@
 [chipflow]
-project_id = 8
+project_name = "test-chip"
+
+[chipflow.top]
+soc = "my_design.design:MySoC"
 
 [chipflow.steps]
-sim = "my_design.steps.sim:MySimStep"
-board = "my_design.steps.board:MyBoardStep"
-silicon = "my_design.steps.silicon:MySiliconStep"
-software = "my_design.steps.software:MySoftwareStep"
+silicon = "chipflow_lib.steps.silicon:SiliconStep"
+
+[chipflow.clocks]
+default = 'sys_clk'
+
+[chipflow.resets]
+default = 'sys_rst_n'
 
 [chipflow.silicon]
-process = "sky130"
-pad_ring = "caravel"
+process = "gf130bcd"
+package = "pga144"
 
 [chipflow.silicon.pads]
-sys_clk   = { type = "clk", loc = "0" }
-sys_rstn  = { type = "i",   loc = "1" }
-uart_tx   = { type = "o",   loc = "2" }
-uart_rx   = { type = "i",   loc = "3" }
-flash_clk = { type = "o",   loc = "4" }
-flash_csn = { type = "o",   loc = "5" }
-flash_d0  = { type = "io",  loc = "6" }
-flash_d1  = { type = "io",  loc = "7" }
-flash_d2  = { type = "io",  loc = "8" }
-flash_d3  = { type = "io",  loc = "9" }
-gpio_0    = { type = "io",  loc = "10" }
-gpio_1    = { type = "io",  loc = "11" }
-gpio_2    = { type = "io",  loc = "12" }
-gpio_3    = { type = "io",  loc = "13" }
-gpio_4    = { type = "io",  loc = "14" }
-gpio_5    = { type = "io",  loc = "15" }
-gpio_6    = { type = "io",  loc = "16" }
-gpio_7    = { type = "io",  loc = "17" }
-btn_0     = { type = "io",  loc = "18" }
-btn_1     = { type = "io",  loc = "19" }
-jtag_tck  = { type = "i",   loc = "33" }
-jtag_tms  = { type = "i",   loc = "34" }
-jtag_tdi  = { type = "i",   loc = "35" }
-jtag_tdo  = { type = "o",   loc = "36" }
+# System
+sys_clk   = { type = "clock", loc = "114" }
+sys_rst_n = { type = "reset", loc = "115" }
+
+[chipflow.silicon.power]
+dvss0        = { type = "power", loc =   "1" }
+dvdd0        = { type = "ground", loc =   "9" }
+vss0         = { type = "power", loc =  "17" }
+vdd0         = { type = "ground", loc =  "25" }
+dvss1        = { type = "power", loc =  "33" }
+dvdd1        = { type = "ground", loc =  "41" }
+vss1         = { type = "power", loc =  "49" }
+vdd1         = { type = "ground", loc =  "57" }
+dvss2        = { type = "power", loc =  "65" }
+dvdd2        = { type = "ground", loc =  "73" }
+vss2         = { type = "power", loc =  "81" }
+vdd2         = { type = "ground", loc =  "89" }
+dvss3        = { type = "power", loc =  "97" }
+dvdd3        = { type = "ground", loc = "105" }
+vss3         = { type = "power", loc = "113" }
+vdd3         = { type = "ground", loc = "121" }
+dvss4        = { type = "power", loc = "129" }
+dvdd4        = { type = "ground", loc = "137" }
diff --git a/docs/index.rst b/docs/index.rst
index a61fc9fe..eaece24e 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -1,9 +1,16 @@
-chipflow-lib documentation
-==========================
+ChipFlow Library Documentation
+------------------------------
+
+.. image: _static/chipflow-logo.svg
+   :width: 200px
+   :class: sd-m-auto
+   :name: landing-page-logo
+
+
+.. rubric: ChipFlow IC Design Platform
 
-Contents
---------
 
 .. toctree::
 
    chipflow-toml-guide
+

From d04d76b3fdbbdecc31f46cc64acd236c38081c58 Mon Sep 17 00:00:00 2001
From: Rob Taylor <rob.taylor@chipflow.io>
Date: Tue, 11 Feb 2025 16:35:47 +0000
Subject: [PATCH 6/6] chore: ignore .coverage

---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index 584bee2d..aa32746c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -9,6 +9,7 @@ __pycache__/
 /.pdm-python
 /.pdm-build
 /.venv
+/.coverage
 
 # pytest
 /.pytest_cache