From 20389bdece379256c13a235b784b4e300169fd46 Mon Sep 17 00:00:00 2001 From: Serge Rabyking Date: Sat, 15 Mar 2025 12:50:34 +0000 Subject: [PATCH 1/4] Added process to the pin lock file --- chipflow_lib/pin_lock.py | 6 +++++- chipflow_lib/platforms/utils.py | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/chipflow_lib/pin_lock.py b/chipflow_lib/pin_lock.py index 9dff907b..f60986bc 100644 --- a/chipflow_lib/pin_lock.py +++ b/chipflow_lib/pin_lock.py @@ -86,6 +86,7 @@ def lock_pins() -> None: oldlock = LockFile.model_validate_json(json_string) print(f"Locking pins: {'using pins.lock' if lockfile.exists() else ''}") + process_name = config["chipflow"]["silicon"]["process"] package_name = config["chipflow"]["silicon"]["package"] if package_name not in PACKAGE_DEFINITIONS: @@ -145,7 +146,10 @@ def lock_pins() -> None: _map, _ = allocate_pins(k, v, pins) port_map.add_ports(component, k, _map) - newlock = LockFile(package=package, port_map=port_map, metadata=interfaces) + newlock = LockFile(process=process_name, + package=package, + port_map=port_map, + metadata=interfaces) with open('pins.lock', 'w') as f: f.write(newlock.model_dump_json(indent=2, serialize_as_any=True)) diff --git a/chipflow_lib/platforms/utils.py b/chipflow_lib/platforms/utils.py index 69cc4abd..e0455fe5 100644 --- a/chipflow_lib/platforms/utils.py +++ b/chipflow_lib/platforms/utils.py @@ -405,6 +405,7 @@ class LockFile(pydantic.BaseModel): port_map: Mapping of components to interfaces to port metadata: Amaranth metadata, for reference """ + process: str package: Package port_map: PortMap metadata: dict From 166d1df5d76de2789e79d01b2d208093f997d23f Mon Sep 17 00:00:00 2001 From: Rob Taylor Date: Sun, 16 Mar 2025 11:28:06 +0000 Subject: [PATCH 2/4] Modify for multiple processes --- chipflow_lib/__init__.py | 10 +++++++--- chipflow_lib/pin_lock.py | 4 ++-- chipflow_lib/platforms/utils.py | 13 ++++++++++++- chipflow_lib/steps/silicon.py | 7 +++---- docs/chipflow-toml-guide.rst | 9 ++++++--- docs/example-chipflow.toml | 5 ++++- tests/fixtures/mock.toml | 6 +++++- 7 files changed, 39 insertions(+), 15 deletions(-) diff --git a/chipflow_lib/__init__.py b/chipflow_lib/__init__.py index 09adb0ba..2c5d91a3 100644 --- a/chipflow_lib/__init__.py +++ b/chipflow_lib/__init__.py @@ -74,13 +74,17 @@ def _ensure_chipflow_root(): "silicon": { "type": "object", "required": [ - "process", + "processes", "package", ], "additionalProperties": False, "properties": { - "process": { - "enum": ["sky130", "gf180", "customer1", "gf130bcd", "ihp_sg13g2"] + "processes": { + "type": "array", + "items": { + "type": "string", + "enum": ["sky130", "gf180", "customer1", "gf130bcd", "ihp_sg13g2"] + } }, "package": { "enum": ["caravel", "cf20", "pga144"] diff --git a/chipflow_lib/pin_lock.py b/chipflow_lib/pin_lock.py index f60986bc..28eb046b 100644 --- a/chipflow_lib/pin_lock.py +++ b/chipflow_lib/pin_lock.py @@ -86,7 +86,7 @@ def lock_pins() -> None: oldlock = LockFile.model_validate_json(json_string) print(f"Locking pins: {'using pins.lock' if lockfile.exists() else ''}") - process_name = config["chipflow"]["silicon"]["process"] + processes = config["chipflow"]["silicon"]["process"] package_name = config["chipflow"]["silicon"]["package"] if package_name not in PACKAGE_DEFINITIONS: @@ -146,7 +146,7 @@ def lock_pins() -> None: _map, _ = allocate_pins(k, v, pins) port_map.add_ports(component, k, _map) - newlock = LockFile(process=process_name, + newlock = LockFile(processes=processes, package=package, port_map=port_map, metadata=interfaces) diff --git a/chipflow_lib/platforms/utils.py b/chipflow_lib/platforms/utils.py index e0455fe5..1bbca861 100644 --- a/chipflow_lib/platforms/utils.py +++ b/chipflow_lib/platforms/utils.py @@ -396,6 +396,17 @@ def get_ports(self, component: str, name: str) -> Dict[str, Port]: return self[component][name] +class Process(enum.Enum): + SKY130 = "sky130" + GF180 = "gf180" + HELVELLYN2 = "helvellyn2" + GF130BCD = "gf130bcd" + IHP_SG13G2 = "ihp_sg13g2" + + def __str__(self): + return f'{self.name}' + + class LockFile(pydantic.BaseModel): """ Representation of a pin lock file. @@ -405,7 +416,7 @@ class LockFile(pydantic.BaseModel): port_map: Mapping of components to interfaces to port metadata: Amaranth metadata, for reference """ - process: str + processes: List[Process] package: Package port_map: PortMap metadata: dict diff --git a/chipflow_lib/steps/silicon.py b/chipflow_lib/steps/silicon.py index 4a393e43..f243a2d7 100644 --- a/chipflow_lib/steps/silicon.py +++ b/chipflow_lib/steps/silicon.py @@ -140,20 +140,19 @@ def submit(self, rtlil_path, *, dry_run=False): for i in range(width): padname = f"{iface}{i}" logger.debug(f"padname={padname}, port={port}, loc={port.pins[i]}, " - f"dir={port.direction}, width={width}") + f"dir={port.direction}, width={width}") pads[padname] = {'loc': port.pins[i], 'type': port.direction.value} else: padname = f"{iface}" logger.debug(f"padname={padname}, port={port}, loc={port.pins[0]}, " - f"dir={port.direction}, width={width}") + f"dir={port.direction}, width={width}") pads[padname] = {'loc': port.pins[0], 'type': port.direction.value} - config = { "dependency_versions": dep_versions, "silicon": { - "process": self.silicon_config["process"], + "process": self.silicon_config["processes"][0], "pad_ring": self.silicon_config["package"], "pads": pads, "power": self.silicon_config.get("power", {}) diff --git a/docs/chipflow-toml-guide.rst b/docs/chipflow-toml-guide.rst index 07d7cbc0..7113588b 100644 --- a/docs/chipflow-toml-guide.rst +++ b/docs/chipflow-toml-guide.rst @@ -57,12 +57,15 @@ You probably won't need to change these if you're starting from an example repos .. code-block:: TOML [chipflow.silicon] - process = "ihp_sg13g2" + processes = [ + "ihp_sg13g2", + "gf130bcd" + ] package = "pga144" -The ``silicon`` section sets the Foundry ``process`` we are targeting for manufacturing, and the physical ``package`` we want to place our design inside. -You'll choose the ``process`` and ``package`` based in the requirements of your design. +The ``silicon`` section sets the Foundry ``processes`` (i.e. PDKs) that we are targeting for manufacturing, and the physical ``package`` we want to place our design inside. +You'll choose the ``processes`` and ``package`` based in the requirements of your design. Available processes ------------------- diff --git a/docs/example-chipflow.toml b/docs/example-chipflow.toml index 3c7c31a5..0cfcd023 100644 --- a/docs/example-chipflow.toml +++ b/docs/example-chipflow.toml @@ -14,7 +14,10 @@ default = 'sys_clk' default = 'sys_rst_n' [chipflow.silicon] -process = "gf130bcd" +processes = [ + "gf130bcd", + "gf130bcd" + ] package = "pga144" [chipflow.silicon.pads] diff --git a/tests/fixtures/mock.toml b/tests/fixtures/mock.toml index 72e319e7..1b9a0cd0 100644 --- a/tests/fixtures/mock.toml +++ b/tests/fixtures/mock.toml @@ -5,7 +5,11 @@ project_name = "proj-name" silicon = "chipflow_lib.steps.silicon:SiliconStep" [chipflow.silicon] -process = "ihp_sg13g2" +processes = [ + "ihp_sg13g2", + "helvellyn2", + "sky130" +] package = "pga144" [chipflow.clocks] From b9e5fabb749f61e720df63f534da1442afc9df04 Mon Sep 17 00:00:00 2001 From: Serge Rabyking Date: Mon, 17 Mar 2025 13:59:25 +0000 Subject: [PATCH 3/4] Updated to have single process in configs for now. --- chipflow_lib/__init__.py | 11 ++++------- chipflow_lib/pin_lock.py | 4 ++-- chipflow_lib/platforms/utils.py | 2 +- chipflow_lib/steps/silicon.py | 2 +- 4 files changed, 8 insertions(+), 11 deletions(-) diff --git a/chipflow_lib/__init__.py b/chipflow_lib/__init__.py index 2c5d91a3..9993d08d 100644 --- a/chipflow_lib/__init__.py +++ b/chipflow_lib/__init__.py @@ -74,17 +74,14 @@ def _ensure_chipflow_root(): "silicon": { "type": "object", "required": [ - "processes", + "process", "package", ], "additionalProperties": False, "properties": { - "processes": { - "type": "array", - "items": { - "type": "string", - "enum": ["sky130", "gf180", "customer1", "gf130bcd", "ihp_sg13g2"] - } + "process": { + "type": "string", + "enum": ["sky130", "gf180", "customer1", "gf130bcd", "ihp_sg13g2"] }, "package": { "enum": ["caravel", "cf20", "pga144"] diff --git a/chipflow_lib/pin_lock.py b/chipflow_lib/pin_lock.py index 28eb046b..f60986bc 100644 --- a/chipflow_lib/pin_lock.py +++ b/chipflow_lib/pin_lock.py @@ -86,7 +86,7 @@ def lock_pins() -> None: oldlock = LockFile.model_validate_json(json_string) print(f"Locking pins: {'using pins.lock' if lockfile.exists() else ''}") - processes = config["chipflow"]["silicon"]["process"] + process_name = config["chipflow"]["silicon"]["process"] package_name = config["chipflow"]["silicon"]["package"] if package_name not in PACKAGE_DEFINITIONS: @@ -146,7 +146,7 @@ def lock_pins() -> None: _map, _ = allocate_pins(k, v, pins) port_map.add_ports(component, k, _map) - newlock = LockFile(processes=processes, + newlock = LockFile(process=process_name, package=package, port_map=port_map, metadata=interfaces) diff --git a/chipflow_lib/platforms/utils.py b/chipflow_lib/platforms/utils.py index 1bbca861..a7f24542 100644 --- a/chipflow_lib/platforms/utils.py +++ b/chipflow_lib/platforms/utils.py @@ -416,7 +416,7 @@ class LockFile(pydantic.BaseModel): port_map: Mapping of components to interfaces to port metadata: Amaranth metadata, for reference """ - processes: List[Process] + process: Process package: Package port_map: PortMap metadata: dict diff --git a/chipflow_lib/steps/silicon.py b/chipflow_lib/steps/silicon.py index f243a2d7..ebc75ec1 100644 --- a/chipflow_lib/steps/silicon.py +++ b/chipflow_lib/steps/silicon.py @@ -152,7 +152,7 @@ def submit(self, rtlil_path, *, dry_run=False): config = { "dependency_versions": dep_versions, "silicon": { - "process": self.silicon_config["processes"][0], + "process": self.silicon_config["process"], "pad_ring": self.silicon_config["package"], "pads": pads, "power": self.silicon_config.get("power", {}) From ed956bf5a221ea61b26b1b0e842a1beca68ffcd5 Mon Sep 17 00:00:00 2001 From: Serge Rabyking Date: Mon, 17 Mar 2025 14:17:06 +0000 Subject: [PATCH 4/4] Updated example chipflow.toml to make tests pass. --- docs/example-chipflow.toml | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/docs/example-chipflow.toml b/docs/example-chipflow.toml index 0cfcd023..3c7c31a5 100644 --- a/docs/example-chipflow.toml +++ b/docs/example-chipflow.toml @@ -14,10 +14,7 @@ default = 'sys_clk' default = 'sys_rst_n' [chipflow.silicon] -processes = [ - "gf130bcd", - "gf130bcd" - ] +process = "gf130bcd" package = "pga144" [chipflow.silicon.pads]