diff --git a/chipflow_lib/platforms/silicon.py b/chipflow_lib/platforms/silicon.py
index f95be78e..7180dfcd 100644
--- a/chipflow_lib/platforms/silicon.py
+++ b/chipflow_lib/platforms/silicon.py
@@ -86,14 +86,12 @@ def __init__(self,
             self._i = Signal(port.width, name=f"{component}_{name}__i")
         if self._direction in (io.Direction.Output, io.Direction.Bidir):
             self._o = Signal(port.width, name=f"{component}_{name}__o")
+        # Only bidir ports have output-enable. Either each line has its own OE, or there's one OE for all the wires
         if self._direction is io.Direction.Bidir:
             if "all_have_oe" in self._options and self._options["all_have_oe"]:
                 self._oe = Signal(port.width, name=f"{component}_{name}__oe", init=-1)
             else:
                 self._oe = Signal(1, name=f"{component}_{name}__oe", init=-1)
-        elif self._direction is io.Direction.Output:
-            # Always create an _oe for output ports
-            self._oe = Signal(1, name=f"{component}_{name}__oe", init=-1)
 
         logger.debug(f"Created SiliconPlatformPort {name}, width={len(port.pins)},dir{self._direction}")
 
@@ -101,30 +99,30 @@ def wire(self, m: Module, interface: PureInterface):
         assert self._direction == interface.signature.direction
         if hasattr(interface, 'i'):
             m.d.comb += interface.i.eq(self.i)
-        for d in ['o', 'oe']:
-            if hasattr(interface, d):
-                m.d.comb += getattr(self, d).eq(getattr(interface, d))
+        if hasattr(interface, 'o'):
+            m.d.comb += self.o.eq(interface.o)
+        if hasattr(interface, 'oe') and self._oe is not None:
+            m.d.comb += self.oe.eq(interface.oe)
 
     @property
-
     def i(self):
         if self._i is None:
             raise AttributeError("SiliconPlatformPort with output direction does not have an "
-                               "input signal")
+                                 "input signal")
         return self._i
 
     @property
     def o(self):
         if self._o is None:
             raise AttributeError("SiliconPlatformPort with input direction does not have an "
-                               "output signal")
+                                 "output signal")
         return self._o
 
     @property
     def oe(self):
         if self._oe is None:
-            raise AttributeError("SiliconPlatformPort with input direction does not have an "
-                               "output enable signal")
+            raise AttributeError("SiliconPlatformPort with output or input direction does not have an "
+                                 "output enable signal")
         return self._oe
 
     @property
@@ -219,6 +217,9 @@ def elaborate(self, platform):
             m.d.comb += i_inv.eq(self.port.i)
         if self.direction in (io.Direction.Output, io.Direction.Bidir):
             m.d.comb += self.port.o.eq(o_inv)
+
+        # Only set oe for bidirectional ports
+        if self.direction is io.Direction.Bidir:
             m.d.comb += self.port.oe.eq(self.oe)
 
         return m
diff --git a/tests/test_silicon_platform_port.py b/tests/test_silicon_platform_port.py
index 68930f4f..db546236 100644
--- a/tests/test_silicon_platform_port.py
+++ b/tests/test_silicon_platform_port.py
@@ -40,7 +40,8 @@ def test_init_output_port(self):
 
         # Test accessing properties
         _ = spp.o  # Should not raise an error
-        _ = spp.oe  # Should not raise an error since we now always have an _oe for outputs
+        with self.assertRaises(AttributeError):
+            _ = spp.oe  # Should raise an error since output ports don't have oe signals
         with self.assertRaises(AttributeError):
             _ = spp.i  # Should raise an error for output port
 
@@ -174,7 +175,7 @@ def __init__(self):
         spp.wire(m, interface)
 
     def test_wire_output(self):
-        # Test wire method with a mock output interface to cover line 105
+        # Test wire method with a mock output interface
         port_obj = Port(type="output", pins=["1", "2"], port_name="test_output",
                          direction="o", options={})
         spp = SiliconPlatformPort("comp", "test_output", port_obj)
@@ -193,7 +194,6 @@ class MockInterface(PureInterface):
             def __init__(self):
                 self.signature = MockSignature()
                 self.o = Signal(2)
-                self.oe = Signal(1)
 
         interface = MockInterface()
         m = Module()
@@ -247,4 +247,4 @@ def test_repr(self):
         self.assertIn("SiliconPlatformPort", repr_str)
         self.assertIn("direction", repr_str)
         self.assertIn("width=3", repr_str)
-        self.assertIn("invert=False", repr_str)
\ No newline at end of file
+        self.assertIn("invert=False", repr_str)