diff --git a/.github/workflows/main.yaml b/.github/workflows/main.yaml index e360c75..8f23a44 100644 --- a/.github/workflows/main.yaml +++ b/.github/workflows/main.yaml @@ -1,21 +1,20 @@ -name: CI - on: push: branches: - 'main' pull_request: - merge_group: +name: CI jobs: - build-upcounter: - runs-on: ubuntu-22.04 + submit: + runs-on: ubuntu-latest + strategy: + matrix: + design: ['upcounter', 'rom', 'sram'] steps: - name: Check out source code uses: actions/checkout@v4 - with: - fetch-depth: 0 - uses: actions/setup-python@v4 with: @@ -28,85 +27,31 @@ jobs: cache-dependency-path: pyproject.toml cache: true - - name: Install dependencies - run: pdm install -d - - - name: Build upcounter + - name: Generate overrides to use current branch if PR + if: github.event_name == 'pull_request' run: | - pdm run chipflow pin lock - pdm run chipflow silicon prepare - pdm run chipflow silicon submit --wait - env: - CHIPFLOW_BACKEND_VERSION: "branch-main" - CHIPFLOW_ROOT: "upcounter" - CHIPFLOW_API_ORIGIN: 'https://build-staging.chipflow.org' - CHIPFLOW_API_KEY_ID: ${{ secrets.CHIPFLOW_API_KEY_ID }} - CHIPFLOW_API_KEY_SECRET: ${{ secrets.CHIPFLOW_API_KEY_SECRET }} + pdm run tools/gen_overrides.py ${{github.head_ref}} > overrides.txt + echo "Generated overrides:" + cat overrides.txt - build-rom: - runs-on: ubuntu-22.04 - steps: - - name: Check out source code - uses: actions/checkout@v4 - with: - fetch-depth: 0 + - name: Relock PDM + if: github.event_name != 'pull_request' + run: pdm lock -d - - uses: actions/setup-python@v4 - with: - python-version: '3.10' - - - name: Set up PDM - uses: pdm-project/setup-pdm@v4 - with: - python-version-file: pyproject.toml - cache-dependency-path: pyproject.toml - cache: true + - name: Relock PDM (PR) + if: github.event_name == 'pull_request' + run: pdm lock -d --override overrides.txt - name: Install dependencies - run: pdm install -d - - - name: Build rom run: | - pdm run chipflow pin lock - pdm run chipflow silicon prepare - pdm run chipflow silicon submit --wait - env: - CHIPFLOW_BACKEND_VERSION: "branch-main" - CHIPFLOW_ROOT: "rom" - CHIPFLOW_API_ORIGIN: 'https://build-staging.chipflow.org' - CHIPFLOW_API_KEY_ID: ${{ secrets.CHIPFLOW_API_KEY_ID }} - CHIPFLOW_API_KEY_SECRET: ${{ secrets.CHIPFLOW_API_KEY_SECRET }} - - build-sram: - runs-on: ubuntu-22.04 - steps: - - name: Check out source code - uses: actions/checkout@v4 - with: - fetch-depth: 0 - - - uses: actions/setup-python@v4 - with: - python-version: '3.10' - - - name: Set up PDM - uses: pdm-project/setup-pdm@v4 - with: - python-version-file: pyproject.toml - cache-dependency-path: pyproject.toml - cache: true + pdm install - - name: Install dependencies - run: pdm install -d + - name: Lock pins + working-directory: ./${{ matrix.design }} + run: pdm run chipflow pin lock - - name: Build sram - run: | - pdm run chipflow pin lock - pdm run chipflow silicon prepare - pdm run chipflow silicon submit --wait + - name: Submit to cloud backend + working-directory: ./${{ matrix.design }} + run: pdm run chipflow silicon submit --wait env: - CHIPFLOW_BACKEND_VERSION: "branch-main" - CHIPFLOW_ROOT: "sram" - CHIPFLOW_API_ORIGIN: 'https://build-staging.chipflow.org' - CHIPFLOW_API_KEY_ID: ${{ secrets.CHIPFLOW_API_KEY_ID }} - CHIPFLOW_API_KEY_SECRET: ${{ secrets.CHIPFLOW_API_KEY_SECRET }} + CHIPFLOW_API_KEY: ${{ secrets.CHIPFLOW_API_KEY}} diff --git a/pyproject.toml b/pyproject.toml index db66ba8..381162d 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -5,9 +5,9 @@ name = "chipflow-test-socs" version = "0.0.0" description = "ChipFlow test designs" authors = [ - {name = "Robert Taylor", email = "rob.taylor@chipflow.io>" }, - {name = "Catherine Zotova", email = "catherine.zotova@chipflow.io>" }, - {name = "Serge Rabyking", email = "serge.rabyking@chipflow.io>" }, + {name = "Robert Taylor", email = "rob.taylor@chipflow.io" }, + {name = "Catherine Zotova", email = "catherine.zotova@chipflow.io" }, + {name = "Serge Rabyking", email = "serge.rabyking@chipflow.io" }, ] license = {file = "LICENSE.md"} diff --git a/rom/design/design.py b/rom/design/design.py index 5043f02..6861d13 100644 --- a/rom/design/design.py +++ b/rom/design/design.py @@ -1,7 +1,7 @@ from amaranth import * from amaranth.lib import wiring from amaranth.lib.wiring import In, Out, flipped, connect -from chipflow_lib.platforms import InputPinSignature, OutputPinSignature +from chipflow_lib.platforms import InputIOSignature, OutputIOSignature import random @@ -9,8 +9,8 @@ __all__ = ["ROMSignature", "ROM"] ROMSignature = wiring.Signature({ - "addr": Out(InputPinSignature(8)), - "data_out": Out(OutputPinSignature(16)), + "addr": Out(InputIOSignature(8)), + "data_out": Out(OutputIOSignature(16)), }) diff --git a/sram/design/design.py b/sram/design/design.py index 3ac0d0d..96d98aa 100644 --- a/sram/design/design.py +++ b/sram/design/design.py @@ -1,17 +1,17 @@ from amaranth import * from amaranth.lib import wiring from amaranth.lib.wiring import In, Out, flipped, connect -from chipflow_lib.platforms import InputPinSignature, OutputPinSignature +from chipflow_lib.platforms import InputIOSignature, OutputIOSignature __all__ = ["SRAMSignature", "SRAM"] SRAMSignature = wiring.Signature({ - "addr": Out(InputPinSignature(12)), - "data_out": Out(OutputPinSignature(16)), - "data_oe": Out(OutputPinSignature(16)), - "data_in": Out(InputPinSignature(16)), - "wr_en": Out(InputPinSignature(1)) + "addr": Out(InputIOSignature(12)), + "data_out": Out(OutputIOSignature(16)), + "data_oe": Out(OutputIOSignature(16)), + "data_in": Out(InputIOSignature(16)), + "wr_en": Out(InputIOSignature(1)) }) diff --git a/tools/gen_overrides.py b/tools/gen_overrides.py new file mode 100644 index 0000000..055a545 --- /dev/null +++ b/tools/gen_overrides.py @@ -0,0 +1,53 @@ +# gen-overrides.py +# /// script +# requires-python = ">=3.10" +# dependencies = [ +# "pyproject-parser", +# "requirements-parser", +# ] +# /// +import os +import subprocess +import sys +import urllib +from pathlib import Path + +from pyproject_parser import PyProject +from requirements.requirement import Requirement + + +rootdir = Path(os.environ["PDM_PROJECT_ROOT"]) + +def get_branch(repo_dir): + """Get the current git branch""" + return subprocess.check_output(['git', 'branch', '--show-current'], text=True).strip() + +def get_remote_branch(repo, branch): + return subprocess.call( + ['git', 'ls-remote', '--exit-code', '--heads', repo, f'refs/heads/{branch}'], + stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL) == 0 + +def gen_overrides(): + if len(sys.argv) > 1: + branch = sys.argv[1] + if branch.startswith("refs/heads/"): + branch = branch[11:] + else: + branch = get_branch(rootdir) + prj = PyProject.load(rootdir / "pyproject.toml") + reqs = prj.project['dependencies'] + git_reqs = [r for r in reqs if r.url and r.url.startswith('git+')] + for r in git_reqs: + parts = urllib.parse.urlparse(r.url, allow_fragments=True) + # remove any branches that might already be there + base = parts.path.rsplit(sep="@",maxsplit=1)[0] + clone_url = urllib.parse.urlunparse(parts._replace(path=base, scheme="https")) + if get_remote_branch(clone_url, branch): + path = f"{parts.path}@{branch}" + else: + path = parts.path + r.url = urllib.parse.urlunparse(parts._replace(path=path)) + print(str(r)) + +if __name__ == "__main__": + gen_overrides() diff --git a/tools/json_compare.py b/tools/json_compare.py new file mode 100644 index 0000000..fa4318e --- /dev/null +++ b/tools/json_compare.py @@ -0,0 +1,42 @@ +import json +import os +import sys +from pathlib import Path +from pprint import pformat + +working_dir = Path(os.environ["PDM_RUN_CWD"] if "PDM_RUN_CWD" in os.environ else "./") + +gold_path = Path(sys.argv[1]) +gate_path = Path(sys.argv[2]) + +gold_path = gold_path if gold_path.is_absolute() else working_dir / gold_path +gate_path = gate_path if gate_path.is_absolute() else working_dir / gate_path + +def on_ci(): + if "CI" in os.environ and os.environ["CI"]: + return True + return False + +def main(): + with open(gold_path, "r") as f: + gold = json.load(f) + with open(gate_path, "r") as f: + gate = json.load(f) + if len(gold["events"]) != len(gate["events"]): + print(f"Failed! Event mismatch: {len(gold['events'])} events in reference, {len(gate['events'])} in test output") + if on_ci(): + print(f"Test Output:\n{pformat(gate)}\n") + print(f"Reference events:\n{pformat(gold)}\n") + return 1 + for ev_gold, ev_gate in zip(gold["events"], gate["events"]): + if ev_gold["peripheral"] != ev_gate["peripheral"] or \ + ev_gold["event"] != ev_gate["event"] or \ + ev_gold["payload"] != ev_gate["payload"]: + print(f"Failed! Reference event {ev_gold} mismatches test event {ev_gate}") + return 1 + + print("Success! Event logs are identical") + return 0 + +if __name__ == "__main__": + main() diff --git a/upcounter/design/design.py b/upcounter/design/design.py index d6e51c5..ca61394 100644 --- a/upcounter/design/design.py +++ b/upcounter/design/design.py @@ -1,15 +1,15 @@ from amaranth import * from amaranth.lib import wiring from amaranth.lib.wiring import In, Out, flipped, connect -from chipflow_lib.platforms import InputPinSignature, OutputPinSignature +from chipflow_lib.platforms import InputIOSignature, OutputIOSignature __all__ = ["CounterSignature", "UpCounter"] CounterSignature = wiring.Signature({ - "limit": Out(InputPinSignature(8)), - "en": Out(InputPinSignature(1)), - "ovf": Out(OutputPinSignature(1)), - "count": Out(OutputPinSignature(8)) + "limit": Out(InputIOSignature(8)), + "en": Out(InputIOSignature(1)), + "ovf": Out(OutputIOSignature(1)), + "count": Out(OutputIOSignature(8)) })