From 35bc0e71935dd07aca8d984d3979ce880e69262a Mon Sep 17 00:00:00 2001 From: Serge Rabyking Date: Thu, 8 May 2025 19:22:07 +0100 Subject: [PATCH 1/3] Updated upcounter design to have top pins be directly specified with PinSignature --- upcounter/design/design.py | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/upcounter/design/design.py b/upcounter/design/design.py index d6e51c5..238f2d1 100644 --- a/upcounter/design/design.py +++ b/upcounter/design/design.py @@ -16,25 +16,26 @@ class UpCounter(wiring.Component): design_name = "upcounter" - def __init__(self): - # define interfaces (for pads connections see design/steps/silicon.py and test_socs_common/silicon.py) - interfaces = { - "pins": Out(CounterSignature), - } - super().__init__(interfaces) + limit: Out(InputPinSignature(8)) + en: Out(InputPinSignature(1)) + ovf: Out(OutputPinSignature(1)) + count: Out(OutputPinSignature(8)) def elaborate(self, platform): m = Module() - pins = self.pins + limit = self.limit + en = self.en + ovf = self.ovf + count = self.count - m.d.comb += pins.ovf.o.eq(pins.count.o == pins.limit.i) + m.d.comb += ovf.o.eq(count.o == limit.i) - with m.If(pins.en.i): - with m.If(pins.ovf.o): - m.d.sync += pins.count.o.eq(0) + with m.If(en.i): + with m.If(ovf.o): + m.d.sync += count.o.eq(0) with m.Else(): - m.d.sync += pins.count.o.eq(pins.count.o + 1) + m.d.sync += count.o.eq(count.o + 1) return m From 3f3b652cc133f2df31f8445a651f253ee663f43a Mon Sep 17 00:00:00 2001 From: Serge Rabyking Date: Thu, 8 May 2025 19:28:05 +0100 Subject: [PATCH 2/3] Removed unused code --- upcounter/design/design.py | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/upcounter/design/design.py b/upcounter/design/design.py index 238f2d1..fe2aa24 100644 --- a/upcounter/design/design.py +++ b/upcounter/design/design.py @@ -1,16 +1,9 @@ from amaranth import * from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out, flipped, connect +from amaranth.lib.wiring import Out from chipflow_lib.platforms import InputPinSignature, OutputPinSignature -__all__ = ["CounterSignature", "UpCounter"] - -CounterSignature = wiring.Signature({ - "limit": Out(InputPinSignature(8)), - "en": Out(InputPinSignature(1)), - "ovf": Out(OutputPinSignature(1)), - "count": Out(OutputPinSignature(8)) -}) +__all__ = ["UpCounter"] class UpCounter(wiring.Component): From f60eae1881179e11aa649ccb4e702781a31d05b1 Mon Sep 17 00:00:00 2001 From: Serge Rabyking Date: Mon, 10 Nov 2025 16:56:08 +0000 Subject: [PATCH 3/3] Synced with chipflow-lib --- sram/chipflow.toml | 35 ++--------------------------------- sram/design/design.py | 14 +++++--------- upcounter/chipflow.toml | 33 ++------------------------------- upcounter/design/design.py | 10 +++++----- 4 files changed, 14 insertions(+), 78 deletions(-) diff --git a/sram/chipflow.toml b/sram/chipflow.toml index 4559275..2acbcd9 100644 --- a/sram/chipflow.toml +++ b/sram/chipflow.toml @@ -7,37 +7,6 @@ soc = "design.design:MySoC" [chipflow.steps] silicon = "chipflow_lib.steps.silicon:SiliconStep" -[chipflow.clocks] -default = 'sys_clk' - -[chipflow.resets] -default = 'sys_rst_n' - [chipflow.silicon] -process = "ihp_sg13g2" -package = "pga144" - -[chipflow.silicon.pads] -# System -sys_clk = { type = "clock", loc = "114" } -sys_rst_n = { type = "reset", loc = "115" } - -[chipflow.silicon.power] -dvss0 = { type = "power", loc = "1" } -dvdd0 = { type = "ground", loc = "9" } -vss0 = { type = "power", loc = "17" } -vdd0 = { type = "ground", loc = "25" } -dvss1 = { type = "power", loc = "33" } -dvdd1 = { type = "ground", loc = "41" } -vss1 = { type = "power", loc = "49" } -vdd1 = { type = "ground", loc = "57" } -dvss2 = { type = "power", loc = "65" } -dvdd2 = { type = "ground", loc = "73" } -vss2 = { type = "power", loc = "81" } -vdd2 = { type = "ground", loc = "89" } -dvss3 = { type = "power", loc = "97" } -dvdd3 = { type = "ground", loc = "105" } -vss3 = { type = "power", loc = "113" } -vdd3 = { type = "ground", loc = "121" } -dvss4 = { type = "power", loc = "129" } -dvdd4 = { type = "ground", loc = "137" } +process = "sky130" +package = "openframe" diff --git a/sram/design/design.py b/sram/design/design.py index 3ac0d0d..a3d09ed 100644 --- a/sram/design/design.py +++ b/sram/design/design.py @@ -1,17 +1,16 @@ from amaranth import * from amaranth.lib import wiring from amaranth.lib.wiring import In, Out, flipped, connect -from chipflow_lib.platforms import InputPinSignature, OutputPinSignature +from chipflow_lib.platforms import InputIOSignature, OutputIOSignature __all__ = ["SRAMSignature", "SRAM"] SRAMSignature = wiring.Signature({ - "addr": Out(InputPinSignature(12)), - "data_out": Out(OutputPinSignature(16)), - "data_oe": Out(OutputPinSignature(16)), - "data_in": Out(InputPinSignature(16)), - "wr_en": Out(InputPinSignature(1)) + "addr": Out(InputIOSignature(12)), + "data_out": Out(OutputIOSignature(8)), + "data_in": Out(InputIOSignature(8)), + "wr_en": Out(InputIOSignature(1)) }) @@ -46,9 +45,6 @@ def elaborate(self, platform): with m.Else(): m.d.sync += self.mem.data_out.o.eq(sram_r.data) - for i in range(self.data_width): - m.d.comb += self.mem.data_oe.o[i].eq(self.mem.wr_en.i) - return m diff --git a/upcounter/chipflow.toml b/upcounter/chipflow.toml index 621105f..df84179 100644 --- a/upcounter/chipflow.toml +++ b/upcounter/chipflow.toml @@ -7,38 +7,9 @@ soc = "design.design:MySoC" [chipflow.steps] silicon = "chipflow_lib.steps.silicon:SiliconStep" -[chipflow.clocks] -default = 'sys_clk' - -[chipflow.resets] -default = 'sys_rst_n' - [chipflow.silicon] process = "ihp_sg13g2" package = "pga144" - -[chipflow.silicon.pads] -# System -sys_clk = { type = "clock", loc = "114" } -sys_rst_n = { type = "reset", loc = "115" } - -[chipflow.silicon.power] -dvss0 = { type = "power", loc = "1" } -dvdd0 = { type = "ground", loc = "9" } -vss0 = { type = "power", loc = "17" } -vdd0 = { type = "ground", loc = "25" } -dvss1 = { type = "power", loc = "33" } -dvdd1 = { type = "ground", loc = "41" } -vss1 = { type = "power", loc = "49" } -vdd1 = { type = "ground", loc = "57" } -dvss2 = { type = "power", loc = "65" } -dvdd2 = { type = "ground", loc = "73" } -vss2 = { type = "power", loc = "81" } -vdd2 = { type = "ground", loc = "89" } -dvss3 = { type = "power", loc = "97" } -dvdd3 = { type = "ground", loc = "105" } -vss3 = { type = "power", loc = "113" } -vdd3 = { type = "ground", loc = "121" } -dvss4 = { type = "power", loc = "129" } -dvdd4 = { type = "ground", loc = "137" } +#process = "sky130" +#package = "openframe" diff --git a/upcounter/design/design.py b/upcounter/design/design.py index fe2aa24..38cd6b0 100644 --- a/upcounter/design/design.py +++ b/upcounter/design/design.py @@ -1,7 +1,7 @@ from amaranth import * from amaranth.lib import wiring from amaranth.lib.wiring import Out -from chipflow_lib.platforms import InputPinSignature, OutputPinSignature +from chipflow_lib.platforms import InputIOSignature, OutputIOSignature __all__ = ["UpCounter"] @@ -9,10 +9,10 @@ class UpCounter(wiring.Component): design_name = "upcounter" - limit: Out(InputPinSignature(8)) - en: Out(InputPinSignature(1)) - ovf: Out(OutputPinSignature(1)) - count: Out(OutputPinSignature(8)) + limit: Out(InputIOSignature(8)) + en: Out(InputIOSignature(1)) + ovf: Out(OutputIOSignature(1)) + count: Out(OutputIOSignature(8)) def elaborate(self, platform): m = Module()