Load from Intel hex file

[dcrawford79]

Is your feature request related to a problem? Please describe.
No

Describe the solution you'd like
Ability to load ram from a .hex records Since the RAM is small,
pasting the .hex record data from the clip board makes sense.
Our use case would be do enter a few code examples from the keyboard, then for the remainder
of our sessions, we'd like to load follow on examples from a window of
a web based assembler.

Though the other ET-3400's require .s19 format, for my purposes intel hex is better as
that is what ASM80.com puts out.

---

From ASM80 with .a68 files such as

;--------------------------------------------------------------------------
; Make the display do loop-d-loops with keys 1-f speed controls
; and key 0 is an exit to the monitor.

SEG_DP .EQU $80
SEG_A .EQU $40
SEG_B .EQU $20
SEG_C .EQU $10
SEG_D .EQU $08
SEG_E .EQU $04
SEG_F .EQU $02
SEG_G .EQU $01
SEGS_ALL .EQU $FF

BIOS_DISPLAY_ADDR .equ $00F0
BIOS_OUTCHR .equ $FE3A
BIOS_GETKEY .equ $FDBB
BIOS_RESET .equ $FC00
DIGIT_ADDR_MSB .EQU $C100
DIGIT_LSB_0 .EQU $6F
DIGIT_OFFSET .EQU $0010
DIGIT_LSB_1 .EQU DIGIT_LSB_0-DIGIT_OFFSET
DIGIT_LSB_2 .EQU DIGIT_LSB_1-DIGIT_OFFSET
DIGIT_LSB_3 .EQU DIGIT_LSB_2-DIGIT_OFFSET
DIGIT_LSB_4 .EQU DIGIT_LSB_3-DIGIT_OFFSET
DIGIT_LSB_5 .EQU DIGIT_LSB_4-DIGIT_OFFSET

;-----------------------------------------------------------------------------------
; PHASE 5: Cycle through all the displays w/ Speed Control
;
.org $0000

CycleDisplaysWithSpeedControl:
JSR CycleDisplays
JSR BIOS_GETKEY ; Is any key pressed?
BCC CycleDisplaysWithSpeedControl ; No Key start over
CMPA #$00 ; $00?
BEQ CheckKeyExit ; Its 0, start over
STAA DelayCount ; Use it- store it in MSB of DelayCount
JMP CycleDisplaysWithSpeedControl ; Key 0 was pressed, reset.

;-----------------------------------------------------------------------------------
; PHASE 4: Cycle through all the displays
;
.org $0020

CycleDisplaysTest:
JSR CycleDisplays
BRA CycleDisplaysTest

CycleDisplays:
LDX # DisplayDIgitLSBList
MoreDisplays:
LDAA 0,X
BEQ CycleDisplaysExit
STAA DisplayAddress+1 ; LSB
STX DisplayDigitListAddress ; save it
LDX DisplayAddress
JSR CycleSegments
LDX DisplayDigitListAddress ;Restore it
INX ; ppint tp mext LSB
BRA MoreDisplays

CycleDisplaysExit:
RTS

CurrentDisplayAddr:
.DW DIGIT_ADDR_MSB+DIGIT_LSB_0 ; First display

DisplayDigitLSBList:
.DB DIGIT_LSB_0,DIGIT_LSB_1,DIGIT_LSB_2,DIGIT_LSB_3,DIGIT_LSB_4,DIGIT_LSB_5,0

; Poke into the LSB and put out the full address.
DisplayAddress:
.DW DIGIT_ADDR_MSB

DisplayDigitListAddress:
.DW $0000

;-----------------------------------------------------------------------------------
; PHASE 3: Cycle segments a-b-c-d-e-f-a with delay
; Display address is in X
; Noting is preseverd.

.org $050

CycleSegmentsTest:
LDX # DIGIT_ADDR_MSB+DIGIT_LSB_0
JSR CycleSegments
BRA CycleSegmentsTest

CycleSegments:
LDAA # SEG_A
NextSeg:
PSHA
JSR DisplaySegmentPaced
PULA
ASRA
CMPA # SEG_G
BEQ CycleSegExit
BRA NextSeg

CycleSegExit:
; Redisplay seg A.
LDAA # SEG_A
JSR DisplaySegmentPaced
; Clear last one no delay
LDAA #$00
JSR DisplaySegment
RTS

; Subroutine to output a 7-seg LED value & Delay
; X passed in has display address, not preserved.
DisplaySegmentPaced:
JSR DisplaySegment
JSR Delay
RTS

; Subroutine to produce a fixed delay
; using a busy loop decrementing X from a fixed value.
; X is preserverd.
Delay:
STX DelayXSave
LDX DelayCount
DelayMore:
BEQ DelayExit
DEX
BRA DelayMore
DelayExit:
LDX DelayXSave
RTS

DelayCount:
.DW $0F00
DelayXSave:
.DW $0000

;-----------------------------------------------------------------------------------
; PHASE 2: Test program to see if we can write a segment
; As a built in .DW if the first display, but if overwritten,
; it will write to any of them.
; Waits for a key press to exit.

.org $0090

DisplaySegmentTest:
LDAA # SEGS_ALL
LDX # DIGIT_ADDR_MSB+DIGIT_LSB_0
JSR DisplaySegment
BRA DisplaySegmentTest

DisplaySegment:
STX BIOS_DISPLAY_ADDR
JSR BIOS_OUTCHR
JSR CheckKey
RTS

;-----------------------------------------------------------------------------------
; PHASE 1: Key Routines & Exit to BIOS

.org $00B0

CheckKeyTest:
JSR CheckKey
BRA CheckKeyTest

CheckKey:
JSR BIOS_GETKEY ; Is any key pressed?
BCC CheckKeyExit ; No Key was pressed
CMPA #$00 ; $00?
BNE CheckKeyExit ; No- so don't reset
JMP BIOS_RESET ; Key 0 was pressed, reset.
CheckKeyExit:
RTS

--- This is available in a wind to cut and past from in a window, intel hex:

:10000000BD0025BDFDBB24F8810027F4978420F0B6
:10002000BD002520FBCE003DA600270E9745DF46EC
:10003000DE44BD0058DE460820EE39C16F6F5F4FC9
:080040003F2F1F00C10000006A
:10005000CEC16FBD005820F8864036BD00713247D2
:100060008101270220F48640BD00718600BD009A00
:1000700039BD009ABD007839DF86DE842703092068
:08008000FBDE86390F000000D1
:1000900086FFCEC16FBD009A20F6DFF0BDFE3ABDEF
:0300A00000B5396F
:1000B000BD00B520FBBDFDBB2407810026037EFCEF
:0200C000003905
:00000001FF

Maybe this shows you my code in the assembler?
https://www.asm80.com/?nfname=Test&nftype=a68#Phase4-a68

[dcrawford79]

I edited it just now to modify the format requested to intex hex records instead of .s19

[dcrawford79]

Please accept .hex records that are not necessarily in ascending address order, such as

:1000B000BD00B520FBBDFDBB2407810026037EFCEF
:0200C000003905
:1000900086FFCEC16FBD009A20F6DFF0BDFE3ABDEF
:0300A00000B5396F
:10005000CEC16FBD005820F8864036BD00713247D2
:100060008101270220F48640BD00718600BD009A00
:1000700039BD009ABD007839DF86DE842703092068
:08008000FBDE86390F000000D1
:10002000BD002520FBCE003DA600270E9745DF46EC
:10003000DE44BD0058DE460820EE39C16F6F5F4FC9
:080040003F2F1F00C10000006A
:10000000BD0025BDFDBB24F8810027B597847E0087
:0100100000EF
:00000001FF

Some tools issue warnings for out of order addresses.

[ChuckTerry]

On the first point, yes, I can implement a memory loader. It may take me a bit because I'm rusty on my file types but I think I planned ahead and coded a loader in, I'll just have to write a transpiler for the different formats. I definitely want hex file support to be on the list. We can likely detect the major .hex variants (I remember some use different end of file markers) easily to reduce confusion when loading.

Out of order addressing will be a simple add once the code injector is built. I keep saying transpiler but it's really just an input stream.

The underlying code that drives the proc cycles on this thing is just a loop that breaks every so often to prevent the browser from crashing. It makes events that heavily rely on clock timing impossible to implement but otherwise has worked quite well. For example, currently the button presses write directly to memory and break out of the main program loop that checks for how long a button is pressed. Pressing the button causes the loop to lag otherwise.

If this is an issue with any programs you intend to load let me know and I'll look into on the fly wasm conversion for finer tuned control. It'll take me a bit on this one, but I'll try to get back to you within the week with something that is at least minimally functional and I can work from there.

Thanks for your suggestions and feature requests btw. This is one of my favorite projects that I haven't touched in a while :)

[dcrawford79]

I'm thrilled you are into continuing this project.
All that sounds good.
One week would be ideal!

I'm planning to use the ET-3400 as the basis for a 45 minute activity class on microprocessors
and machine language. We'll load a few sections of code by hand, then throw the whole example
in by hex if you have it functioning.

The first go is on June 4. If I could get hex loading by then it would be a big plus.

Accurate timing to the hardware is not important with our use case.

[dcrawford79]

Any progress?

Final version of my sample file for now...

;-----------------------------------------------------------------------------------
; __ ____ __
; / / ____ ____ ____ / __ ___ ___ / / ____ ____ ____
; / / / __ / __ / __ \ / / / / _ / _ \ / / / __ / __ / __
; / // // / // / // / / // / _/ / / // // / // / // /
; //_/_/ ./ //_/_/ //_/_/ ./
; // /_/
; Author: Douglas Crawford
; Contact: Douglas.C.Crawford@outlook.com
;
; This program cyles through each display in sequence where the
; outer LED segments are lit in a circle pattern.
; The 0 key exits the program back to the monitor
; Digits 1-F control the speed.
;
; This was assembled with https://www.asm80.com/ and run in the
; David Santos ET3400 v0.2 beta.zip simulator from the files area.
; The .Hex file was converted to .s19 with srec_cat.exe from
; srecord 1.65..0 at https://srecord.sourceforge.net/
; Note: I found a bug in the older "sharp" simulator where the condition
; codes on an LDX were being set only by the LSB of the load instead of
; the full 16 bit value.
;
; The program is Written in 5 phases that builds up to the full program.
;
; Phases 1-4 have a test program and a callalble routine.
; Each phase is testable by performing a "DO" at the starting address
; of the phase. (See the .org statement)
; The test routine calls the "callable" routine to test it's funcationality.
; The "callable" routines are then used by the subsequent phase to build
; up the functionality until phase 5 completes the program..
;
; Each phase introduces new documentation and EQU defines necessary
; to accomplish the phase. Each phase builds on the former phase definitions.
;
;-----------------------
;
; NOTE to ET-3400 knowlegeable folks: You may wonder why
; I didn't use REDIS to initialize the internal display pointer
; and depend on the auto-incrementing feature of OUTCHR to move
; in sequence Well it is because it is cumbersome.
; OUTCHAR's auto-increment is a pain to use when you want to stay on the
; same display. OUTCHR in my opinion should have not auto-incremented, and
; a routine should have been provided to advance to the next display.
; Look how unclear the sample code is in the SAMPLE 1 in the manual.
; The way that the code has to "back up" to stay writing on the same display
; is rather unkind to the new student. ; I defy anyone first looking at
; that code to understand what is going on, let along explaining that example
; to a person just approaching the ET-3400.
;
; So instead this program, in phase 3, implements its own
; system for managaing which display is being written to.
; The code still uses OUTCHR, but since we have our own list of the
; display addresses, it is easy and clear how the code is setting the address
; prior to each call to OUTCHR. The upshot is that it is clear and
; easy to understand what is going on.

;-----------------------------------------------------------------------------------
; ___ __ ___
; / _ / / ___ ____ ___ < /
; / / _ / _ `(-</ -) / /
;// ////_,//_/ //
;
; Tests for the 0 key being pressed and exit to the monitor
; Since the display is cleared when a "DO" is done,
; the test presents a blank display, and waits for the 0 key to be hit.
;
; These Resources we use from the Monitor ROM
MON_GETKEY .equ $FDBB
MON_RESET .equ $FC00

.org $00B0

CheckKeyTest:
JSR CheckKey
BRA CheckKeyTest

CheckKey:
JSR MON_GETKEY ; Is any key pressed?
BCC CheckKeyExit ; No Key was pressed
CMPA #$00 ; $00?
BNE CheckKeyExit ; No- so don't reset
JMP MON_RESET ; Key 0 was pressed, reset.
CheckKeyExit:
RTS

;-----------------------------------------------------------------------------------
; ___ __ ___
; / _ / / ___ ____ ___ |_ |
; / / _ / _ `(-</ -) / __/
;// ////_,//_/ /___/
;
; This routine lights up all the segments of a display digit.
; The test routine oeprates on the first digit.
; The callable routine expects the memory address of a digit to
; be in the X register.
;

; The digits are implemented on the ET-3400 as...
; You write the address to a specific place and call the output routine
; with a byte in A that has bits set for the digits to light up.
; All bits on lights all segments.
SEGS_ALL_ON .EQU $FF
MON_DISPLAY_ADDR .EQU $00F0 ; Controls what digit to access
MON_OUTCHR_RTN .EQU $FE3A
DIGIT_ADDR_BASE .EQU $C100 ; base address of LED displays
DIGIT_LSB_0 .EQU $6F ; lower 8 bits of leftmost display

.org $0090

DisplaySegmentTest:
LDAA # SEGS_ALL_ON
LDX # DIGIT_ADDR_BASE+DIGIT_LSB_0
JSR DisplaySegment
BRA DisplaySegmentTest

DisplaySegment:
STX MON_DISPLAY_ADDR
JSR MON_OUTCHR_RTN
JSR CheckKey
RTS

;-----------------------------------------------------------------------------------
; ___ __ ____
; / _ / / ___ ____ ___ |_ /
; / / _ / _ `(-</ -) / <
;// ////_,//_/ /___/
;
; This phase makes one cycle around a display top, right, bottom, left top.
; Since the segments are represented in the bits of a byte, and A through
; F are all in a row, Arithetic Shift Right is used to step through the
; segments. Then segment A is residplayed, and then cleared.
; This phase introduces a delay routine which is implemented as a
; 16 bit initial value loaded from RAM into X and decremented down to 0.
;
; The test routine operates on the first display.
; The callable routine expects the display address to be in the X register.
;
; Standard Seven Segment Display Definition
;
; A
; --------
; | |
; F | | B
; | G |
; --------
; | |
; E | | C
; | |
; -------- DP
; D
;
; Bit order of the segment controls
; used by the ET-3400.
;
;----------------------------------
;| DP | A | B | C | D | E | F | G |
;----------------------------------
;
; Define the byte bit patters of the
SEG_DP .EQU $80
SEG_A .EQU $40
SEG_B .EQU $20
SEG_C .EQU $10
SEG_D .EQU $08
SEG_E .EQU $04
SEG_F .EQU $02
SEG_G .EQU $01
SEGS_ALL .EQU $FF

DELAY_COUNT_X .EQU $6F00

.org $050

CycleSegmentsTest:
LDX # DIGIT_ADDR_BASE+DIGIT_LSB_0
JSR CycleSegments
BRA CycleSegmentsTest

CycleSegments:
LDAA # SEG_A
NextSeg:
PSHA
JSR DisplaySegmentPaced
PULA
ASRA
CMPA # SEG_G
BEQ CycleSegExit
BRA NextSeg

CycleSegExit:
; Redisplay seg A.
LDAA # SEG_A
JSR DisplaySegmentPaced
; Clear last one no delay
LDAA #$00
JSR DisplaySegment
RTS

; Subroutine to output a 7-seg LED value & Delay
; X passed in has display address, not preserved.
DisplaySegmentPaced:
JSR DisplaySegment
JSR Delay
RTS

; Subroutine to produce a fixed delay
; using a busy loop decrementing X from a fixed value.
; X is preserverd.
Delay:
STX DelayXSave
LDX DelayCount
DelayMore:
BEQ DelayExit
DEX
BRA DelayMore
DelayExit:
LDX DelayXSave
RTS

DelayCount:
.DW $0F00
DelayXSave:
.DW $0000

;-----------------------------------------------------------------------------------
; ___ __ ____
; / _ / / ___ ____ ___ / / /
; / / _ / _ `(-</ -) / /
;// ////_,//_/ //
;
; This phase applies the loop of phase 3 across all 6 displays.
;
; There is a fixed offset in the addresses of the displays
; However, the addresses of each display from left to right
; are decending addresses- That's unintuitive!
; So this phase creates a memory list of the LSB of the
; addresses stored in left to right order.
; The order is decending, but accessed by list order
; the displays are referenced left to right.
; To form the full 16 bit address, a 16 bit
; value in RAM is employed. The value initialized with the
; base address. The LSB value is written filled with a
; byte from the list. After that LSB value is written,
; the RAM value is then loaded into the X register forming
; the full address of the display of interest.
; The address of the display is formed, and the
; the Phase 3 routine is called using that address as a
; parameter in the X

DIGIT_OFFSET .EQU $0010
DIGIT_LSB_1 .EQU DIGIT_LSB_0-DIGIT_OFFSET
DIGIT_LSB_2 .EQU DIGIT_LSB_1-DIGIT_OFFSET
DIGIT_LSB_3 .EQU DIGIT_LSB_2-DIGIT_OFFSET
DIGIT_LSB_4 .EQU DIGIT_LSB_3-DIGIT_OFFSET
DIGIT_LSB_5 .EQU DIGIT_LSB_4-DIGIT_OFFSET

; PHASE 4: Cycle through all the displays
;
.org $0020

CycleDisplaysTest:
JSR CycleDisplays
BRA CycleDisplaysTest

CycleDisplays:
LDX # DisplayLSBList ; Start at beginning of list.

MoreDisplays:
STX DisplayListElementAddress ; save list element address item for later.
LDAA 0,X ; Fetch an LSB from the list.
BEQ CycleDisplaysExit ; If LSB is 0, its the end, so exit.
STAA DisplayAddress+1 ; Put LSB in LSB of 16 bit address in RAM.
LDX DisplayAddress ; Load 16bit address into X.
JSR CycleSegments ; Use phase 3 to cycle segments.
LDX DisplayListElementAddress ; Restore the list element address
INX ; Add 1 to adress tp mext LSB element.
BRA MoreDisplays ; Repeat to the end of the list.

CycleDisplaysExit:
RTS

; Array list of the LSB's of each address in sequence left to right. 0 terminated.
DisplayLSBList:
.DB DIGIT_LSB_0,DIGIT_LSB_1,DIGIT_LSB_2,DIGIT_LSB_3,DIGIT_LSB_4,DIGIT_LSB_5,0

; Address of the current element in the list of LSBs.
DisplayListElementAddress:
.DW DIGIT_ADDR_BASE

; Where we build the 16bit address if a display.
; The LSB is populated with an LSB from the list.
DisplayAddress:
.DW DIGIT_ADDR_BASE

;-----------------------------------------------------------------------------------
; ____ __ ______
; / __ / /_ ____ _________ / /
; / // / __ / __ `/ / _ \ / \
; / / / / / // ( ) __/ / /
; // // //_,/_/_/ /___/
;
;
; THe final phase finishes the program with adding the abilty to control
; the speed of the looping with the hex keys 1-F
; The hex value of the key $01 to $0F is writting to the high
; byte of the 16 bit counter initialization value of the Phase 3 Delay routine.
;
.org $0000

CycleDisplaysWithSpeedControl:
JSR CycleDisplays
JSR MON_GETKEY ; Is any key pressed?
BCC CycleDisplaysWithSpeedControl ; No Key start over
CMPA #$00 ; is it key 0?
BEQ CheckKeyExit ; Its 0, start over
STAA DelayCount ; Its 1-F, store it in MSB of DelayCount
JMP CycleDisplaysWithSpeedControl ; Rinse & Repeat

;---------------------------------------------------------------------------------------------------------
:1000B000BD00B520FBBDFDBB2407810026037EFCEF
:0200C000003905
:1000900086FFCEC16FBD009A20F6DFF0BDFE3ABDEF
:0300A00000B5396F
:10005000CEC16FBD005820F8864036BD0072320C0C
:10006000468101270220F38640BD00728600BD0054
:100070009A39BD009ABD007939DF87DE85270309EB
:0900800020FBDE87390F000000AF
:10002000BD002520FBCE003BDF42A600270C9745F4
:10003000DE44BD0058DE420820EE396F5F4F3F2F8F
:060040001F00C100C10019
:10000000BD0025BDFDBB24F8810027B597857E0086
:0100100000EF
:00000001FF

[ChuckTerry]

Alright, so S-record files will be a fairly easy add since I'm already familiar with the format. I don't expect Intel's format to be much of a jump after that. I've renamed this to indicate "Intel Hex" and I've created another issue for S-record files. The current plan is to:

1. Surface the Autoloader (This is already coded, just not visible on the front-end).
2. Implement .s19 loading via a menu (via text input or file upload).
3. Implement Intel .hex loading via a menu (via text input or file upload).
4. Implement Ctrl + V quick loading from clipboard without dealing with a menu.

The Autoloader currently takes a Program String in this format:

 Program String    :    [Leading Address] <Byte 0> <Byte 1> ... <Byte n>
Leading Address    :    <Address High> <Address Low> <ASCII Space>

So, my current plan is to transpile to that format from .hex, .s19, and any others we need to support in the future.