fix(ram): make verilog write behavior match simulator (#817)

Co-authored-by: Vivek Ray <123629919+092vk@users.noreply.github.com>

Author: aindree-2005

src/simulator/src/sequential/RAM.js

@@ -329,7 +329,7 @@ export default class RAM extends CircuitElement {
         assign dout = mem[addr];
     
         always @ (*) begin
-        if (!we)
+        if (we)
             mem[addr] = din;
         end
     endmodule

v1/src/simulator/src/sequential/RAM.js

@@ -329,7 +329,7 @@ export default class RAM extends CircuitElement {
         assign dout = mem[addr];
     
         always @ (*) begin
-        if (!we)
+        if (we)
             mem[addr] = din;
         end
     endmodule