mfd: clsic: Increase post-reset delay and add one for runtime_resume

 It can take up to 2ms for the codec to become responsive after reset
 has been release or DCVDD has risen.  The current sleeps were on the
 optimistic side, so increase them, and also add one after DCVDD has
 been enabled in runtime_resume.

 Reference tacna change id I72fd445892769f20532bc187a66357582072bb4b

Change-Id: I381b3ff0edea3fd275c45930586878e1d25a5f0d
Signed-off-by: Andrew Ford <[email protected]>

Author: afordcirrus

drivers/mfd/clsic/clsic-core.c

@@ -60,7 +60,7 @@ static void clsic_disable_hard_reset(struct clsic *clsic)
 {
 	if (clsic->reset_gpio) {
 		gpiod_set_value_cansleep(clsic->reset_gpio, 1);
-		usleep_range(1000, 2000);
+		usleep_range(2000, 3000);
 	}
 }
 
@@ -90,6 +90,7 @@ static bool clsic_wait_for_boot_done(struct clsic *clsic)
 void clsic_soft_reset(struct clsic *clsic)
 {
 	regmap_write(clsic->regmap, TACNA_SFT_RESET, CLSIC_SOFTWARE_RESET_CODE);
+	usleep_range(2000, 3000);
 	clsic_wait_for_boot_done(clsic);
 }
 
@@ -1003,6 +1004,8 @@ static int clsic_runtime_resume(struct device *dev)
 		return ret;
 	}
 
+	usleep_range(2000, 3000);
+
 	if (force_reset) {
 		if (clsic->reset_gpio)
 			clsic_hard_reset(clsic);