mfd: tacna: Do a PM runtime get for some 32k clock sources

MCLK1 and the internally derived SYSCLK are not on the always on domain
and as such we need to keep the chip enabled to provide the 32k clock if
those sources are used.

Change-Id: I47ebd7bfdc718964ab235188c8d2da7ae6de539c
Signed-off-by: Charles Keepax <[email protected]>

Author: charleskeepax

drivers/mfd/tacna-core.c

@@ -582,8 +582,22 @@ static int tacna_configure_clk32k(struct tacna *tacna)
 		}
 		break;
 	case TACNA_32KZ_MCLK1:
-	case TACNA_32KZ_MCLK2:
 	case TACNA_32KZ_SYSCLK:
+		switch (tacna->type) {
+		case CS48L31:
+		case CS48L32:
+		case CS48L33:
+			break;
+		default:
+			ret = pm_runtime_get_sync(tacna->dev);
+			if (ret)
+				dev_err(tacna->dev,
+					"Failed to enable chip for 32kHz clock: %d\n",
+					ret);
+			break;
+		}
+		/* Intentional fall-through */
+	case TACNA_32KZ_MCLK2:
 		mclk_src = tacna->pdata.clk32k_src - 1;
 		break;
 	default: