Skip to content

Commit a94a4b3

Browse files
charleskeepaxcharleskeepax
committed
mfd: tacna: Remove some unused registers
Change-Id: I1a74f015de7ed36b7da91822997b9533a4d06d3e Signed-off-by: Charles Keepax <[email protected]>
1 parent 5884d47 commit a94a4b3

File tree

3 files changed

+0
-146
lines changed

3 files changed

+0
-146
lines changed

‎drivers/mfd/cs47l96-tables.c‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -198,8 +198,6 @@ static const struct reg_default cs47l96_reg_default[] = {
198198
{ 0x00004a18, 0x00000000 }, /* OUTPUT_AEC_ENABLE_1 */
199199
{ 0x00004a20, 0x00000000 }, /* OUTPUT_AEC_CONTROL_1 */
200200
{ 0x00004a24, 0x00000000 }, /* OUTPUT_NG_CONTROL_1 */
201-
{ 0x00004c14, 0x00000033 }, /* EDRE_ENABLE */
202-
{ 0x00004c18, 0x00000000 }, /* EDRE_MANUAL */
203201
{ 0x00005000, 0x00000000 }, /* OUTH_ENABLE_1 */
204202
{ 0x00005100, 0x20000000 }, /* OUTH_CONFIG_1 */
205203
{ 0x00005104, 0x000000c0 }, /* OUTHL_VOLUME_1 */
@@ -907,11 +905,9 @@ static const struct reg_default cs47l96_reg_default[] = {
907905
{ 0x0000fc24, 0x00002020 }, /* US3AO_CONTROL */
908906
{ 0x0000fc28, 0x00000000 }, /* US3AO_DET_CONTROL */
909907
{ 0x00010004, 0x00000000 }, /* AO_CTRL2 */
910-
{ 0x00017008, 0x00000000 }, /* DSP1_CTRL_SETUP */
911908
{ 0x00017208, 0x00000000 }, /* DSP1AO_CTRL_SETUP */
912909
{ 0x00017554, 0x00000000 }, /* CODEC_AO_BRIDGE_ERR_HADDR_ERR */
913910
{ 0x00017558, 0x00000000 }, /* AO_CODEC_BRIDGE_ERR_HADDR_ERR */
914-
{ 0x00017560, 0x00000003 }, /* FLL_DSP_CTRL */
915911
{ 0x00017580, 0x00000000 }, /* IN_PDMCLK_SEL */
916912
{ 0x00017584, 0x00000000 }, /* AUXPDM_SWM_SEL */
917913
{ 0x00017588, 0x00000000 }, /* ASP2_OUT5_SEL */
@@ -1205,8 +1201,6 @@ static bool cs47l96_readable_register(struct device *dev, unsigned int reg)
12051201
case TACNA_OUTPUT_AEC_STATUS_1:
12061202
case TACNA_OUTPUT_AEC_CONTROL_1:
12071203
case TACNA_OUTPUT_NG_CONTROL_1:
1208-
case TACNA_EDRE_ENABLE:
1209-
case TACNA_EDRE_MANUAL:
12101204
case TACNA_OUTH_ENABLE_1:
12111205
case TACNA_OUTH_CONFIG_1:
12121206
case TACNA_OUTHL_VOLUME_1:
@@ -1854,11 +1848,9 @@ static bool cs47l96_readable_register(struct device *dev, unsigned int reg)
18541848
case TACNA_US3AO_CONTROL:
18551849
case TACNA_US3AO_DET_CONTROL:
18561850
case TACNA_AO_CTRL2:
1857-
case TACNA_DSP1_CTRL_SETUP:
18581851
case TACNA_DSP1AO_CTRL_SETUP:
18591852
case TACNA_CODEC_AO_BRIDGE_ERR_HADDR_ERR:
18601853
case TACNA_AO_CODEC_BRIDGE_ERR_HADDR_ERR:
1861-
case TACNA_FLL_DSP_CTRL:
18621854
case TACNA_IN_PDMCLK_SEL:
18631855
case TACNA_AUXPDM_SWM_SEL:
18641856
case TACNA_ASP2_OUT5_SEL:

‎drivers/mfd/cs48l32-tables.c‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -376,8 +376,6 @@ static const struct reg_default cs48l32_reg_default[] = {
376376
{ 0x0000c000, 0x00000000 }, /* PWM_DRIVE_1 */
377377
{ 0x0000c004, 0x00000100 }, /* PWM_DRIVE_2 */
378378
{ 0x0000c008, 0x00000100 }, /* PWM_DRIVE_3 */
379-
{ 0x00017008, 0x00000000 }, /* DSP1_CTRL_SETUP */
380-
{ 0x00017560, 0x00000000 }, /* FLL_DSP_CTRL */
381379
{ 0x00018000, 0x00000000 }, /* IRQ1_CFG */
382380
{ 0x00018110, 0xffffffff }, /* IRQ1_MASK_1 */
383381
{ 0x00018114, 0xfffffff7 }, /* IRQ1_MASK_2 */
@@ -792,7 +790,6 @@ static bool cs48l32_readable_register(struct device *dev, unsigned int reg)
792790
case TACNA_PWM_DRIVE_1:
793791
case TACNA_PWM_DRIVE_2:
794792
case TACNA_PWM_DRIVE_3:
795-
case TACNA_DSP1_CTRL_SETUP:
796793
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_0:
797794
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_1:
798795
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_2:
@@ -835,7 +832,6 @@ static bool cs48l32_readable_register(struct device *dev, unsigned int reg)
835832
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_5:
836833
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_6:
837834
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7:
838-
case TACNA_FLL_DSP_CTRL:
839835
case TACNA_IRQ1_CFG:
840836
case TACNA_IRQ1_STATUS:
841837
case TACNA_IRQ1_EINT_1 ... TACNA_IRQ1_EINT_11:

‎include/linux/mfd/tacna/registers.h‎

Lines changed: 0 additions & 134 deletions
Original file line numberDiff line numberDiff line change
@@ -260,8 +260,6 @@
260260
#define TACNA_FRF_COEFF_5L_2 0x4b84
261261
#define TACNA_FRF_COEFF_5R_1 0x4b88
262262
#define TACNA_FRF_COEFF_5R_2 0x4b8c
263-
#define TACNA_EDRE_ENABLE 0x4c14
264-
#define TACNA_EDRE_MANUAL 0x4c18
265263
#define TACNA_OUTH_ENABLE_1 0x5000
266264
#define TACNA_OUTH_CONFIG_1 0x5100
267265
#define TACNA_OUTHL_VOLUME_1 0x5104
@@ -989,19 +987,6 @@
989987
#define TACNA_ANC_L_CTRL_2 0xca04
990988
#define TACNA_ANC_L_CTRL_3 0xca08
991989
#define TACNA_ANC_L_CTRL_66 0xcb08
992-
#define TACNA_ANC_L_FBF_CONTROL 0xcb20
993-
#define TACNA_ANC_L_FBF_GAIN 0xcb24
994-
#define TACNA_ANC_L_FBF_COEFF_UPDATE 0xcb28
995-
#define TACNA_ANC_L_FBF_COEFF2_1 0xcb30
996-
#define TACNA_ANC_L_FBF_COEFF128_127 0xcc2c
997-
#define TACNA_ANC_L_FB_IIR_CONTROL 0xcc60
998-
#define TACNA_ANC_L_FB_IIR_COEFF_UPDATE 0xcc64
999-
#define TACNA_ANC_L_FB_IIR1_B0 0xcc6c
1000-
#define TACNA_ANC_L_FB_IIR2_A2 0xcc98
1001-
#define TACNA_ANC_L_FF_IIR_CONTROL 0xcd20
1002-
#define TACNA_ANC_L_FF_IIR_COEFF_UPDATE 0xcd24
1003-
#define TACNA_ANC_L_FF_IIR1_B0 0xcd2c
1004-
#define TACNA_ANC_L_FF_IIR2_A2 0xcd5c
1005990
#define TACNA_AOBRIDGE1_ENABLE 0xd800
1006991
#define TACNA_AOBRIDGE2_ENABLE 0xd804
1007992
#define TACNA_AOBRIDGE1_CH1_CTRL 0xd80c
@@ -1098,7 +1083,6 @@
10981083
#define TACNA_US3AO_CONTROL 0xfc24
10991084
#define TACNA_US3AO_DET_CONTROL 0xfc28
11001085
#define TACNA_AO_CTRL2 0x10004
1101-
#define TACNA_DSP1_CTRL_SETUP 0x17008
11021086
#define TACNA_DSP1_XM_SRAM_IBUS_SETUP_0 0x1700c
11031087
#define TACNA_DSP1_XM_SRAM_IBUS_SETUP_1 0x17010
11041088
#define TACNA_DSP1_XM_SRAM_IBUS_SETUP_2 0x17014
@@ -1176,7 +1160,6 @@
11761160
#define TACNA_DSP1AO_CTRL_SETUP 0x17208
11771161
#define TACNA_CODEC_AO_BRIDGE_ERR_HADDR_ERR 0x17554
11781162
#define TACNA_AO_CODEC_BRIDGE_ERR_HADDR_ERR 0x17558
1179-
#define TACNA_FLL_DSP_CTRL 0x17560
11801163
#define TACNA_IN_PDMCLK_SEL 0x17580
11811164
#define TACNA_AUXPDM_SWM_SEL 0x17584
11821165
#define TACNA_ASP2_OUT5_SEL 0x17588
@@ -4369,42 +4352,6 @@
43694352
#define TACNA_AEC_LOOPBACK1_SRC_SHIFT 0
43704353
#define TACNA_AEC_LOOPBACK1_SRC_WIDTH 4
43714354

4372-
/* (0x4c14) EDRE_ENABLE */
4373-
#define TACNA_EDRE_OUT2L_THR1_ENA 0x00000008
4374-
#define TACNA_EDRE_OUT2L_THR1_ENA_MASK 0x00000008
4375-
#define TACNA_EDRE_OUT2L_THR1_ENA_SHIFT 3
4376-
#define TACNA_EDRE_OUT2L_THR1_ENA_WIDTH 1
4377-
#define TACNA_EDRE_OUT2R_THR1_ENA 0x00000004
4378-
#define TACNA_EDRE_OUT2R_THR1_ENA_MASK 0x00000004
4379-
#define TACNA_EDRE_OUT2R_THR1_ENA_SHIFT 2
4380-
#define TACNA_EDRE_OUT2R_THR1_ENA_WIDTH 1
4381-
#define TACNA_EDRE_OUT1L_THR1_ENA 0x00000002
4382-
#define TACNA_EDRE_OUT1L_THR1_ENA_MASK 0x00000002
4383-
#define TACNA_EDRE_OUT1L_THR1_ENA_SHIFT 1
4384-
#define TACNA_EDRE_OUT1L_THR1_ENA_WIDTH 1
4385-
#define TACNA_EDRE_OUT1R_THR1_ENA 0x00000001
4386-
#define TACNA_EDRE_OUT1R_THR1_ENA_MASK 0x00000001
4387-
#define TACNA_EDRE_OUT1R_THR1_ENA_SHIFT 0
4388-
#define TACNA_EDRE_OUT1R_THR1_ENA_WIDTH 1
4389-
4390-
/* (0x4c18) EDRE_MANUAL */
4391-
#define TACNA_EDRE_OUT2L_MANUAL 0x00000008
4392-
#define TACNA_EDRE_OUT2L_MANUAL_MASK 0x00000008
4393-
#define TACNA_EDRE_OUT2L_MANUAL_SHIFT 3
4394-
#define TACNA_EDRE_OUT2L_MANUAL_WIDTH 1
4395-
#define TACNA_EDRE_OUT2R_MANUAL 0x00000004
4396-
#define TACNA_EDRE_OUT2R_MANUAL_MASK 0x00000004
4397-
#define TACNA_EDRE_OUT2R_MANUAL_SHIFT 2
4398-
#define TACNA_EDRE_OUT2R_MANUAL_WIDTH 1
4399-
#define TACNA_EDRE_OUT1L_MANUAL 0x00000002
4400-
#define TACNA_EDRE_OUT1L_MANUAL_MASK 0x00000002
4401-
#define TACNA_EDRE_OUT1L_MANUAL_SHIFT 1
4402-
#define TACNA_EDRE_OUT1L_MANUAL_WIDTH 1
4403-
#define TACNA_EDRE_OUT1R_MANUAL 0x00000001
4404-
#define TACNA_EDRE_OUT1R_MANUAL_MASK 0x00000001
4405-
#define TACNA_EDRE_OUT1R_MANUAL_SHIFT 0
4406-
#define TACNA_EDRE_OUT1R_MANUAL_WIDTH 1
4407-
44084355
/* (0x4a24) OUTPUT_NG_CONTROL_1 */
44094356
#define TACNA_NGATE_HOLD_MASK 0x00000030
44104357
#define TACNA_NGATE_HOLD_SHIFT 4
@@ -7521,53 +7468,6 @@
75217468
#define TACNA_ANC_L_MIC_SRC_SHIFT 2
75227469
#define TACNA_ANC_L_MIC_SRC_WIDTH 2
75237470

7524-
/* (0xcb20) ANC_L_FBF_CONTROL */
7525-
#define TACNA_ANCMON_L_EN_MASK 0x00000060
7526-
#define TACNA_ANCMON_L_EN_SHIFT 5
7527-
#define TACNA_ANCMON_L_EN_WIDTH 2
7528-
#define TACNA_ANC_L_FBF_DST_MASK 0x00000018
7529-
#define TACNA_ANC_L_FBF_DST_SHIFT 3
7530-
#define TACNA_ANC_L_FBF_DST_WIDTH 2
7531-
#define TACNA_ANC_L_FBF_SRC_MASK 0x00000006
7532-
#define TACNA_ANC_L_FBF_SRC_SHIFT 1
7533-
#define TACNA_ANC_L_FBF_SRC_WIDTH 2
7534-
#define TACNA_ANC_L_FBF_EN 0x00000001
7535-
#define TACNA_ANC_L_FBF_EN_MASK 0x00000001
7536-
#define TACNA_ANC_L_FBF_EN_SHIFT 0
7537-
#define TACNA_ANC_L_FBF_EN_WIDTH 1
7538-
7539-
/* (0xcb24) ANC_L_FBF_GAIN */
7540-
#define TACNA_ANC_L_FBF_GAIN_MASK 0x00000fff
7541-
#define TACNA_ANC_L_FBF_GAIN_SHIFT 0
7542-
#define TACNA_ANC_L_FBF_GAIN_WIDTH 12
7543-
7544-
/* (0xcb28) ANC_L_FBF_COEFF_UPDATE */
7545-
#define TACNA_ANC_L_FBF_COEFF_UPD 0x00000001
7546-
#define TACNA_ANC_L_FBF_COEFF_UPD_MASK 0x00000001
7547-
#define TACNA_ANC_L_FBF_COEFF_UPD_SHIFT 0
7548-
#define TACNA_ANC_L_FBF_COEFF_UPD_WIDTH 1
7549-
7550-
/* (0xcc60) ANC_L_FB_IIR_control */
7551-
#define TACNA_ANC_L_FB_IIR_EN_MASK 0x00000003
7552-
#define TACNA_ANC_L_FB_IIR_EN_SHIFT 0
7553-
#define TACNA_ANC_L_FB_IIR_EN_WIDTH 2
7554-
7555-
/* (0xcc64) ANC_L_FB_IIR_coeff_update */
7556-
#define TACNA_ANC_L_FB_IIR_COEFF_UPD 0x00000001
7557-
#define TACNA_ANC_L_FB_IIR_COEFF_UPD_MASK 0x00000001
7558-
#define TACNA_ANC_L_FB_IIR_COEFF_UPD_SHIFT 0
7559-
#define TACNA_ANC_L_FB_IIR_COEFF_UPD_WIDTH 1
7560-
/* (0xcd20) ANC_L_FF_IIR_control */
7561-
#define TACNA_ANC_L_FF_IIR_EN_MASK 0x00000003
7562-
#define TACNA_ANC_L_FF_IIR_EN_SHIFT 0
7563-
#define TACNA_ANC_L_FF_IIR_EN_WIDTH 2
7564-
7565-
/* (0xcd24) ANC_L_FF_IIR_coeff_update */
7566-
#define TACNA_ANC_L_FF_IIR_COEFF_UPD 0x00000001
7567-
#define TACNA_ANC_L_FF_IIR_COEFF_UPD_MASK 0x00000001
7568-
#define TACNA_ANC_L_FF_IIR_COEFF_UPD_SHIFT 0
7569-
#define TACNA_ANC_L_FF_IIR_COEFF_UPD_WIDTH 1
7570-
75717471
/* (0xd800) AOBRIDGE1_ENABLE */
75727472
#define TACNA_AOBRIDGE1_CH8_EN 0x00000080
75737473
#define TACNA_AOBRIDGE1_CH8_EN_MASK 0x00000080
@@ -8483,16 +8383,6 @@
84838383
#define TACNA_SECURE_MODE_SHIFT 0
84848384
#define TACNA_SECURE_MODE_WIDTH 1
84858385

8486-
/* (0x17008) DSP1_CTRL_SETUP */
8487-
#define TACNA_DSP1_MBIST_SWITCH 0x00000002
8488-
#define TACNA_DSP1_MBIST_SWITCH_MASK 0x00000002
8489-
#define TACNA_DSP1_MBIST_SWITCH_SHIFT 1
8490-
#define TACNA_DSP1_MBIST_SWITCH_WIDTH 1
8491-
#define TACNA_DSP1_TDR_EN 0x00000001
8492-
#define TACNA_DSP1_TDR_EN_MASK 0x00000001
8493-
#define TACNA_DSP1_TDR_EN_SHIFT 0
8494-
#define TACNA_DSP1_TDR_EN_WIDTH 1
8495-
84968386
/* (0x1700c) DSP1_XM_SRAM_IBUS_SETUP_0 */
84978387
#define TACNA_DSP1_XM_SRAM_IBUS_E_PWD_N 0x00000002
84988388
#define TACNA_DSP1_XM_SRAM_IBUS_E_PWD_N_MASK 0x00000002
@@ -8903,16 +8793,6 @@
89038793
#define TACNA_AO_CODEC_BRIDGE_ERR_HADDR_ERR_SHIFT 0
89048794
#define TACNA_AO_CODEC_BRIDGE_ERR_HADDR_ERR_WIDTH 32
89058795

8906-
/* (0x17560) FLL_DSP_CTRL */
8907-
#define TACNA_FLL2_DSPCLK_SEL 0x00000002
8908-
#define TACNA_FLL2_DSPCLK_SEL_MASK 0x00000002
8909-
#define TACNA_FLL2_DSPCLK_SEL_SHIFT 1
8910-
#define TACNA_FLL2_DSPCLK_SEL_WIDTH 1
8911-
#define TACNA_FLL1_DSPCLK_SEL 0x00000001
8912-
#define TACNA_FLL1_DSPCLK_SEL_MASK 0x00000001
8913-
#define TACNA_FLL1_DSPCLK_SEL_SHIFT 0
8914-
#define TACNA_FLL1_DSPCLK_SEL_WIDTH 1
8915-
89168796
/* (0x17580) IN_PDMCLK_SEL */
89178797
#define TACNA_IN3_PDMCLK_SEL 0x00000004
89188798
#define TACNA_IN3_PDMCLK_SEL_MASK 0x00000004
@@ -8946,20 +8826,6 @@
89468826
#define TACNA_ASP2_OUT5_SEL_SHIFT 0
89478827
#define TACNA_ASP2_OUT5_SEL_WIDTH 1
89488828

8949-
/* (0x17560) FLL_DSP_CTRL */
8950-
#define TACNA_FLL3_DSPCLK_SEL 0x00000004
8951-
#define TACNA_FLL3_DSPCLK_SEL_MASK 0x00000004
8952-
#define TACNA_FLL3_DSPCLK_SEL_SHIFT 2
8953-
#define TACNA_FLL3_DSPCLK_SEL_WIDTH 1
8954-
#define TACNA_FLL2_DSPCLK_SEL 0x00000002
8955-
#define TACNA_FLL2_DSPCLK_SEL_MASK 0x00000002
8956-
#define TACNA_FLL2_DSPCLK_SEL_SHIFT 1
8957-
#define TACNA_FLL2_DSPCLK_SEL_WIDTH 1
8958-
#define TACNA_FLL1_DSPCLK_SEL 0x00000001
8959-
#define TACNA_FLL1_DSPCLK_SEL_MASK 0x00000001
8960-
#define TACNA_FLL1_DSPCLK_SEL_SHIFT 0
8961-
#define TACNA_FLL1_DSPCLK_SEL_WIDTH 1
8962-
89638829
/* (0x17590) CHIP_CTRL1 */
89648830
#define TACNA_CIF3_ASYNC_STS_MASK 0x00000300
89658831
#define TACNA_CIF3_ASYNC_STS_SHIFT 8

0 commit comments

Comments
 (0)