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charleskeepaxcharleskeepax
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ASoC: cs48l32: Update handling of DSP memory enables
Switch to a system using a start and end address for each block of memory enable registers. As these registers move around from chip to chip it is better to use a system that allows us to define less registers. Change-Id: I5b1f0637c1a7cb6fe049149f733c359785605a44 Signed-off-by: Charles Keepax <[email protected]>
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5 files changed

+34
-592
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5 files changed

+34
-592
lines changed

‎drivers/mfd/cs48l32-tables.c‎

Lines changed: 6 additions & 84 deletions
Original file line numberDiff line numberDiff line change
@@ -790,48 +790,9 @@ static bool cs48l32_readable_register(struct device *dev, unsigned int reg)
790790
case TACNA_PWM_DRIVE_1:
791791
case TACNA_PWM_DRIVE_2:
792792
case TACNA_PWM_DRIVE_3:
793-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_0:
794-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_1:
795-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_2:
796-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_3:
797-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_4:
798-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_5:
799-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_6:
800-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_7:
801-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_8:
802-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_9:
803-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_10:
804-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_11:
805-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_12:
806-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_13:
807-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_14:
808-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_15:
809-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_16:
810-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_17:
811-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_18:
812-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_19:
813-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_20:
814-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_21:
815-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_22:
816-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_23:
817-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24:
818-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0:
819-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_1:
820-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_2:
821-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_3:
822-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_4:
823-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_5:
824-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_6:
825-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_7:
826-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8:
827-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0:
828-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_1:
829-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_2:
830-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_3:
831-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_4:
832-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_5:
833-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_6:
834-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7:
793+
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24:
794+
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8:
795+
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7:
835796
case TACNA_IRQ1_CFG:
836797
case TACNA_IRQ1_STATUS:
837798
case TACNA_IRQ1_EINT_1 ... TACNA_IRQ1_EINT_11:
@@ -864,48 +825,9 @@ static bool cs48l32_volatile_register(struct device *dev, unsigned int reg)
864825
case TACNA_INPUT_STATUS:
865826
case TACNA_INPUT_CONTROL3:
866827
case TACNA_FX_STATUS:
867-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_0:
868-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_1:
869-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_2:
870-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_3:
871-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_4:
872-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_5:
873-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_6:
874-
case TACNA_DSP1_XM_SRAM_IBUS_SETUP_7:
875-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_8:
876-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_9:
877-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_10:
878-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_11:
879-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_12:
880-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_13:
881-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_14:
882-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_15:
883-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_16:
884-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_17:
885-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_18:
886-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_19:
887-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_20:
888-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_21:
889-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_22:
890-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_23:
891-
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24:
892-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0:
893-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_1:
894-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_2:
895-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_3:
896-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_4:
897-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_5:
898-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_6:
899-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_7:
900-
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8:
901-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0:
902-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_1:
903-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_2:
904-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_3:
905-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_4:
906-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_5:
907-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_6:
908-
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7:
828+
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24:
829+
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8:
830+
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7:
909831
case TACNA_IRQ1_STATUS:
910832
case TACNA_IRQ1_EINT_1 ... TACNA_IRQ1_EINT_11:
911833
case TACNA_IRQ1_STS_1 ... TACNA_IRQ1_STS_11:

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