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lhezlhez
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opencl: initial q8_0 mv_id
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3 files changed

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‎ggml/src/ggml-opencl/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,7 @@ set(GGML_OPENCL_KERNELS
8585
mul_mv_q8_0_f32
8686
mul_mv_mxfp4_f32
8787
mul_mv_id_q4_0_f32_8x_flat
88+
mul_mv_id_q8_0_f32
8889
mul_mv_id_mxfp4_f32
8990
mul_mm_f32_f32_l4_lm
9091
mul_mm_f16_f32_l4_lm

‎ggml/src/ggml-opencl/ggml-opencl.cpp‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -402,6 +402,7 @@ struct ggml_backend_opencl_context {
402402
cl_program program_conv_2d_f16_f32;
403403
cl_program program_tsembd;
404404
cl_program program_mul_mv_id_q4_0_f32_8x_flat;
405+
cl_program program_mul_mv_id_q8_0_f32;
405406
cl_program program_mul_mv_id_mxfp4_f32;
406407
cl_program program_mul_mm_f32_f32_l4_lm;
407408
cl_program program_mul_mm_f16_f32_l4_lm;
@@ -470,6 +471,7 @@ struct ggml_backend_opencl_context {
470471
cl_kernel kernel_conv_2d_f16_f32;
471472
cl_kernel kernel_timestep_embedding;
472473
cl_kernel kernel_mul_mv_id_q4_0_f32_8x_flat;
474+
cl_kernel kernel_mul_mv_id_q8_0_f32;
473475
cl_kernel kernel_mul_mv_id_mxfp4_f32;
474476
cl_kernel kernel_mul_mm_f32_f32_l4_lm;
475477
cl_kernel kernel_mul_mm_f16_f32_l4_lm;
@@ -1729,6 +1731,22 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx, ggml_cl_ve
17291731
GGML_LOG_CONT(".");
17301732
}
17311733

1734+
// mul_mv_id_q8_0_f32
1735+
{
1736+
#ifdef GGML_OPENCL_EMBED_KERNELS
1737+
const std::string kernel_src {
1738+
#include "mul_mv_id_q8_0_f32.cl.h"
1739+
};
1740+
#else
1741+
const std::string kernel_src = read_file("mul_mv_id_q8_0_f32.cl");
1742+
#endif
1743+
backend_ctx->program_mul_mv_id_q8_0_f32 =
1744+
build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts);
1745+
1746+
CL_CHECK((backend_ctx->kernel_mul_mv_id_q8_0_f32 = clCreateKernel(backend_ctx->program_mul_mv_id_q8_0_f32, "kernel_mul_mv_id_q8_0_f32", &err), err));
1747+
GGML_LOG_CONT(".");
1748+
}
1749+
17321750
// mul_mv_id_mxfp4_f32
17331751
{
17341752
#ifdef GGML_OPENCL_EMBED_KERNELS
@@ -2748,6 +2766,7 @@ static bool ggml_opencl_supports_op(ggml_backend_dev_t dev, const struct ggml_te
27482766
return false;
27492767
case GGML_OP_MUL_MAT_ID:
27502768
if (op->src[0]->type == GGML_TYPE_Q4_0 ||
2769+
op->src[0]->type == GGML_TYPE_Q8_0 ||
27512770
op->src[0]->type == GGML_TYPE_MXFP4) {
27522771
if (op->src[1]->type == GGML_TYPE_F32) {
27532772
return ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]);
@@ -6997,6 +7016,46 @@ static void ggml_cl_mul_mat_id(ggml_backend_t backend, const ggml_tensor * src0,
69977016

69987017
break;
69997018
}
7019+
case GGML_TYPE_Q8_0: {
7020+
kernel = backend_ctx->kernel_mul_mv_id_q8_0_f32;
7021+
7022+
if (backend_ctx->gpu_family == INTEL) {
7023+
sgs = 16;
7024+
nsg = 2;
7025+
ndst = 4;
7026+
} else if (backend_ctx->gpu_family == ADRENO) {
7027+
sgs = 64;
7028+
nsg = 2;
7029+
ndst = 8;
7030+
ndst = 4;
7031+
} else {
7032+
GGML_ASSERT(false && "TODO: Unknown GPU");
7033+
}
7034+
7035+
CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device));
7036+
CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0));
7037+
CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device));
7038+
CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1));
7039+
CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device));
7040+
CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2));
7041+
CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device));
7042+
CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd));
7043+
CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00));
7044+
CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01));
7045+
CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01));
7046+
CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02));
7047+
CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne11));
7048+
CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12));
7049+
CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11));
7050+
CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12));
7051+
CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne20));
7052+
CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne21));
7053+
CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb21));
7054+
CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &ne0));
7055+
CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne1));
7056+
7057+
break;
7058+
}
70007059
case GGML_TYPE_MXFP4: {
70017060
kernel = backend_ctx->kernel_mul_mv_id_mxfp4_f32;
70027061

‎ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32.cl‎

Lines changed: 140 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,140 @@
1+
#pragma OPENCL EXTENSION cl_khr_fp16 : enable
2+
3+
#ifdef cl_intel_subgroups
4+
#pragma OPENCL EXTENSION cl_intel_subgroups : enable
5+
#else
6+
#pragma OPENCL EXTENSION cl_khr_subgroups : enable
7+
#endif
8+
9+
#ifdef cl_intel_required_subgroup_size
10+
#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable
11+
#define INTEL_GPU 1
12+
#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16)))
13+
#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32)))
14+
#elif defined(cl_qcom_reqd_sub_group_size)
15+
#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable
16+
#define ADRENO_GPU 1
17+
#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half")))
18+
#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full")))
19+
#endif
20+
21+
#define QK8_0 32
22+
typedef struct {
23+
half d; // delta
24+
char qs[QK8_0]; // quants
25+
} block_q8_0;
26+
27+
#define NB_Q8_0 8
28+
29+
#ifdef INTEL_GPU
30+
#define N_R0_Q8_0 4 // number of rows each subgroup works on
31+
#define N_SG_Q8_0 2 // number of subgroups in a work group
32+
#define N_SIMDWIDTH 16 // subgroup size
33+
#elif defined (ADRENO_GPU)
34+
#define N_R0_Q8_0 4
35+
#define N_SG_Q8_0 2
36+
#define N_SIMDWIDTH 64
37+
#endif
38+
39+
#ifdef INTEL_GPU
40+
REQD_SUBGROUP_SIZE_16
41+
#elif defined (ADRENO_GPU)
42+
REQD_SUBGROUP_SIZE_64
43+
#endif
44+
kernel void kernel_mul_mv_id_q8_0_f32(
45+
global char * src0,
46+
ulong offset0,
47+
global char * src1,
48+
ulong offset1,
49+
global char * src2,
50+
ulong offset2,
51+
global char * dst,
52+
ulong offsetd,
53+
int ne00,
54+
int ne01,
55+
ulong nb01,
56+
ulong nb02,
57+
int ne11,
58+
int ne12,
59+
ulong nb11,
60+
ulong nb12,
61+
int ne20,
62+
int ne21,
63+
ulong nb21,
64+
int ne0,
65+
int ne1
66+
) {
67+
src0 = (global char *)((global char *)src0 + offset0);
68+
src1 = (global char *)((global char *)src1 + offset1);
69+
src2 = (global char *)((global char *)src2 + offset2);
70+
dst = (global char *)((global char *)dst + offsetd);
71+
72+
int iid1 = get_group_id(2)/ne20;
73+
int idx = get_group_id(2)%ne20;
74+
75+
int i02 = ((global int *) (src2 + iid1*nb21))[idx];
76+
77+
int i11_ = idx % ne11;
78+
int i12_ = iid1;
79+
80+
int i1 = idx;
81+
int i2 = i12_;
82+
83+
global char * src0_cur = src0 + i02*nb02;
84+
global char * src1_cur = src1 + i11_*nb11 + i12_*nb12;
85+
86+
global char * dst_cur = dst + (i1*ne0 + i2*ne1*ne0)*sizeof(float);
87+
88+
int nb = ne00/QK8_0;
89+
90+
int r0 = get_group_id(0);
91+
int r1 = get_group_id(1);
92+
93+
int first_row = (r0*N_SG_Q8_0 + get_sub_group_id()) * N_R0_Q8_0;
94+
95+
ulong offset_src1 = r1*nb11;
96+
global float * y = (global float *) (src1_cur + offset_src1);
97+
98+
// pointers to src0 rows
99+
global block_q8_0 * ax[N_R0_Q8_0];
100+
for (int row = 0; row < N_R0_Q8_0; ++row) {
101+
ulong offset_src0 = (first_row + row)*nb01;
102+
ax[row] = (global block_q8_0 *) ((global char *) src0_cur + offset_src0);
103+
}
104+
105+
float yl[NB_Q8_0];
106+
float sumf[N_R0_Q8_0] = { 0.f };
107+
108+
const short ix = get_sub_group_local_id()/4;
109+
const short il = get_sub_group_local_id()%4;
110+
111+
global float * yb = y + ix*QK8_0 + il*NB_Q8_0;
112+
113+
// each thread handles NB_Q8_0 quants at a time
114+
for (int ib = ix; ib < nb; ib += N_SIMDWIDTH/4) {
115+
for (short i = 0; i < NB_Q8_0; ++i) {
116+
yl[i] = yb[i];
117+
}
118+
119+
for (short row = 0; row < N_R0_Q8_0; row++) {
120+
global char * qs = ax[row][ib].qs + il*NB_Q8_0;
121+
float sumq = 0.f;
122+
for (short iq = 0; iq < NB_Q8_0; ++iq) {
123+
sumq += qs[iq] * yl[iq];
124+
}
125+
sumf[row] += sumq*ax[row][ib].d;
126+
}
127+
128+
yb += N_SIMDWIDTH*NB_Q8_0;
129+
}
130+
131+
global float * dst_f32 = (global float *) dst_cur + (ulong)r1*ne0;
132+
133+
for (int row = 0; row < N_R0_Q8_0; ++row) {
134+
float tot = sub_group_reduce_add(sumf[row]);
135+
136+
if (get_sub_group_local_id() == 0 && first_row + row < ne01) {
137+
dst_f32[first_row + row] = tot;
138+
}
139+
}
140+
}

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