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| 1 | +#include "ch32fun.h" |
| 2 | +#include <stdio.h> |
| 3 | + |
| 4 | +#define PIN_CS PC1 |
| 5 | +// Useful to determine the cycle duration with a scope. Goes high the moment CS goes low, and back to low at the last |
| 6 | +// action within the while loop. Can be removed otherwise. |
| 7 | +#define PIN_OUT PC3 |
| 8 | + |
| 9 | +volatile uint8_t buffer_miso[4]; |
| 10 | +volatile uint8_t spi_miso_index = 0; |
| 11 | +volatile uint8_t buffer_mosi[4]; |
| 12 | +volatile uint8_t spi_mosi_index = 0; |
| 13 | + |
| 14 | +typedef enum |
| 15 | +{ |
| 16 | + STATE_IDLE = 0, |
| 17 | + STATE_RECEIVING = 1, |
| 18 | + STATE_RECEIVED = 2, |
| 19 | + STATE_SENDING = 3, |
| 20 | + STATE_SENT = 4, |
| 21 | +} SpiState; |
| 22 | + |
| 23 | +volatile SpiState spi_state = STATE_IDLE; |
| 24 | + |
| 25 | +void wait_for_state( SpiState desired_state ) |
| 26 | +{ |
| 27 | + while ( spi_state != desired_state ) |
| 28 | + { |
| 29 | + } |
| 30 | +} |
| 31 | + |
| 32 | +static uint8_t SPI_read_8() |
| 33 | +{ |
| 34 | + return SPI1->DATAR; |
| 35 | +} |
| 36 | + |
| 37 | +static void SPI_write_8( uint8_t data ) |
| 38 | +{ |
| 39 | + SPI1->DATAR = data; |
| 40 | +} |
| 41 | + |
| 42 | +void SPI_Configure() |
| 43 | +{ |
| 44 | + // reset control register |
| 45 | + SPI1->CTLR1 = 0; |
| 46 | + |
| 47 | + // Enable GPIO Port C and SPI peripheral |
| 48 | + RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_SPI1; |
| 49 | + |
| 50 | + // PC5 is SCLK |
| 51 | + funPinMode( PC5, GPIO_CFGLR_IN_FLOAT ); |
| 52 | + |
| 53 | + // PC6 is MOSI |
| 54 | + funPinMode( PC6, GPIO_CFGLR_IN_FLOAT ); |
| 55 | + |
| 56 | + // PC7 is MISO |
| 57 | + funPinMode( PC7, GPIO_Speed_2MHz | GPIO_CNF_OUT_PP_AF ); |
| 58 | + |
| 59 | + // Configure SPI |
| 60 | + SPI1->CTLR1 |= SPI_CPHA_1Edge | SPI_CPOL_Low | SPI_Mode_Slave | SPI_BaudRatePrescaler_2 | SPI_DataSize_8b; |
| 61 | + SPI1->CTLR1 |= SPI_Direction_2Lines_FullDuplex; |
| 62 | + SPI1->CTLR1 |= CTLR1_SPE_Set; |
| 63 | +} |
| 64 | + |
| 65 | +void SPI1_IRQHandler( void ) __attribute__( ( interrupt ) ); |
| 66 | +void SPI1_IRQHandler( void ) |
| 67 | +{ |
| 68 | + if ( !( SPI1->STATR & SPI_STATR_RXNE ) ) |
| 69 | + { |
| 70 | + return; |
| 71 | + } |
| 72 | + |
| 73 | + // Read received data first to clear RXNE. This is important: not reading the data register can leave RXNE set and |
| 74 | + // prevent further proper IRQ handling. |
| 75 | + uint8_t received = SPI_read_8(); |
| 76 | + if ( spi_state == STATE_SENDING ) |
| 77 | + { |
| 78 | + // When sending, the master clocks data in, and we should provide the next |
| 79 | + // MISO byte for the next clock. Write after reading the incoming byte. |
| 80 | + if ( spi_miso_index < sizeof( buffer_miso ) ) |
| 81 | + { |
| 82 | + SPI_write_8( buffer_miso[spi_miso_index++] ); |
| 83 | + if ( spi_miso_index >= sizeof( buffer_miso ) ) |
| 84 | + { |
| 85 | + spi_state = STATE_SENT; |
| 86 | + } |
| 87 | + } |
| 88 | + else |
| 89 | + { |
| 90 | + spi_state = STATE_SENT; |
| 91 | + } |
| 92 | + } |
| 93 | + else if ( spi_state == STATE_RECEIVING ) |
| 94 | + { |
| 95 | + // Store byte when in receiving state |
| 96 | + buffer_mosi[spi_mosi_index++] = received; |
| 97 | + if ( spi_mosi_index > sizeof( buffer_mosi ) ) |
| 98 | + { |
| 99 | + spi_mosi_index = 0; |
| 100 | + } |
| 101 | + if ( spi_mosi_index == 4 ) |
| 102 | + { |
| 103 | + spi_state = STATE_RECEIVED; |
| 104 | + } |
| 105 | + } |
| 106 | +} |
| 107 | + |
| 108 | +void send() |
| 109 | +{ |
| 110 | + spi_miso_index = 0; |
| 111 | + // Transition to sending: briefly disable RXNE interrupt to avoid the ISR |
| 112 | + // writing 0x00 while we flip state and preload the response bytes. |
| 113 | + SPI1->CTLR2 &= ~SPI_CTLR2_RXNEIE; |
| 114 | + spi_state = STATE_SENDING; |
| 115 | + // Preload the first MISO byte so the master reads the intended first byte. |
| 116 | + if ( spi_miso_index < sizeof( buffer_miso ) ) |
| 117 | + { |
| 118 | + SPI_write_8( buffer_miso[spi_miso_index++] ); |
| 119 | + } |
| 120 | + |
| 121 | + SPI1->CTLR2 |= SPI_CTLR2_RXNEIE; |
| 122 | + wait_for_state( STATE_SENT ); |
| 123 | +} |
| 124 | + |
| 125 | + |
| 126 | +int main() |
| 127 | +{ |
| 128 | + SystemInit(); |
| 129 | + printf( "--- init ---\n" ); |
| 130 | + |
| 131 | + funGpioInitAll(); |
| 132 | + |
| 133 | + funPinMode( PIN_CS, GPIO_CFGLR_IN_PUPD ); |
| 134 | + funPinMode( PIN_OUT, GPIO_Speed_10MHz | GPIO_CNF_OUT_PP ); |
| 135 | + |
| 136 | + SPI_Configure(); |
| 137 | + NVIC_EnableIRQ( SPI1_IRQn ); |
| 138 | + while ( 1 ) |
| 139 | + { |
| 140 | + if ( funDigitalRead( PIN_CS ) ) |
| 141 | + { |
| 142 | + continue; |
| 143 | + } |
| 144 | + |
| 145 | + funDigitalWrite( PIN_OUT, FUN_HIGH ); |
| 146 | + SPI_write_8( 0x00 ); |
| 147 | + // Enable the RXNE interrupt only when CS is low, and we are ready to receive; to avoid unnecessary IRQs. |
| 148 | + // Not exactly necessary, but if the CPU needs to do other things while CS is high, this ensures it will not be, |
| 149 | + // well, interrupted. |
| 150 | + SPI1->CTLR2 |= SPI_CTLR2_RXNEIE; |
| 151 | + spi_mosi_index = 0; |
| 152 | + spi_state = STATE_RECEIVING; |
| 153 | + wait_for_state( STATE_RECEIVED ); |
| 154 | + buffer_miso[0] = buffer_mosi[0]; |
| 155 | + buffer_miso[1] = buffer_mosi[1]; |
| 156 | + buffer_miso[2] = 0xBE; |
| 157 | + buffer_miso[3] = 0xEF; |
| 158 | + send(); |
| 159 | + while ( !funDigitalRead( PIN_CS ) ) |
| 160 | + { |
| 161 | + } |
| 162 | + |
| 163 | + spi_state = STATE_IDLE; |
| 164 | + printf( "RX/MOSI(%d):", 4 ); |
| 165 | + for ( uint8_t i = 0; i < 4; i++ ) |
| 166 | + { |
| 167 | + printf( " %02X", buffer_mosi[i] ); |
| 168 | + } |
| 169 | + |
| 170 | + printf( " | TX/MISO(%d):", 4 ); |
| 171 | + for ( uint8_t i = 0; i < 4; i++ ) |
| 172 | + { |
| 173 | + printf( " %02X", buffer_miso[i] ); |
| 174 | + } |
| 175 | + printf( "\n" ); |
| 176 | + SPI1->CTLR2 &= ~SPI_CTLR2_RXNEIE; |
| 177 | + funDigitalWrite( PIN_OUT, FUN_LOW ); |
| 178 | + } |
| 179 | +} |
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