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Merge pull request cnlohr#857 from monte-monte/master
Add Coremark to projects
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‎.gitmodules‎

Whitespace-only changes.

‎projects/coremark/Makefile‎

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all : flash
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TARGET:=coremark
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# TARGET_MCU:=CH32V006
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# TARGET_MCU:=CH32X035
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# TARGET_MCU:=CH32V103
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# TARGET_MCU:=CH32V203
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# TARGET_MCU_PACKAGE:=CH32V203F8 #64K version
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# TARGET_MCU:=CH32V208
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# TARGET_MCU_PACKAGE:=CH32V208WBU6
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# TARGET_MCU:=CH32V307
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TARGET_MCU:=CH570
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TARGET_MCU_PACKAGE:=CH570D
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# TARGET_MCU:=CH585
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# TARGET_MCU_PACKAGE:=CH585F
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COREMARK:=coremark
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ENABLE_FPU:=0
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CORE_ITERATIONS=4000 #Standard is 4K if you get runs less than 10s increase this number
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CORE_DATA_SIZE=2000 #Will result in this much RAM use
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CORE_MEM_METHOD=0 #0 - STATIC, 1 - HEAP, 2 - STACK
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CORE_MEM_STR="STATIC"
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LDFLAGS+=
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# OPT_FLAGS:=-O3 -funroll-all-loops -finline-limit=600 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling -fno-code-hoisting
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# OPT_FLAGS:=-Os -flto -ffunction-sections -fdata-sections -fmessage-length=0 -msmall-data-limit=8
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OPT_FLAGS:=-O3
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COREMARK_CFLAGS=$(CFLAGS_ARCH) -DTARGET_MCU=$(TARGET_MCU) -DMCU_PACKAGE=$(MCU_PACKAGE) -static-libgcc -I$(NEWLIB) -I$(CH32FUN) -nostdlib -I. -Wall $(EXTRA_CFLAGS) -I$(COREMARK) -DCOMPILER_FLAGS=\""$(OPT_FLAGS)"\" -DITERATIONS=$(CORE_ITERATIONS) -DTOTAL_DATA_SIZE=$(CORE_DATA_SIZE) -DMEM_METHOD=$(CORE_MEM_METHOD) -DMEM_LOCATION=\"$(CORE_MEM_STR)\" -DMAIN_HAS_NOARGC -ffreestanding $(OPT_FLAGS)
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include ../../ch32fun/ch32fun.mk
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CFLAGS+=-ffreestanding
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COREMARK_FILES=core_portme.c $(COREMARK)/core_list_join.c $(COREMARK)/core_main.c $(COREMARK)/core_matrix.c $(COREMARK)/core_state.c $(COREMARK)/core_util.c
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RAM_LD_FILE:=generated_$(TARGET_MCU_PACKAGE)_RAM.ld
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$(RAM_LD_FILE):
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$(PREFIX)-gcc -E -P -x c -DTARGET_MCU=$(TARGET_MCU) -DMCU_PACKAGE=$(MCU_PACKAGE) -DTARGET_MCU_LD=$(TARGET_MCU_LD) -DTARGET_MCU_MEMORY_SPLIT=$(TARGET_MCU_MEMORY_SPLIT) app_in_ram.ld > $(RAM_LD_FILE)
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coremark.elf:
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$(PREFIX)-gcc -c -o ch32fun.o $(SYSTEM_C) $(CFLAGS)
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$(PREFIX)-gcc -c -o printf.o printf.c $(CFLAGS)
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$(PREFIX)-gcc -o $@ ch32fun.o printf.o $(COREMARK_FILES) $(COREMARK_CFLAGS) $(LDFLAGS)
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# $(PREFIX)-gcc -o $@ ch32fun.o $(COREMARK_FILES) $(COREMARK_CFLAGS) $(LDFLAGS)
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runfromram: LINKER_SCRIPT:=$(RAM_LD_FILE)
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runfromram: $(RAM_LD_FILE) $(TARGET).bin
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$(MINICHLINK)/minichlink -ks 0x10 0x80000001 -s 0x10 0x80000003 -s 0x10 0x80000001 -s 0x18 0 -w $(TARGET).bin 0x20000000 -s 0x04 0x20000000 -s 0x17 0x002307b1 -s 0x10 0x40000001 -T
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flash: cv_flash
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clean:
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rm -rf ch32fun.o printf.o $(TARGET).elf $(TARGET).bin $(TARGET)_ext.bin $(TARGET).hex $(TARGET).lst $(TARGET).map $(TARGET).hex $(GENERATED_LD_FILE) $(RAM_LD_FILE) || true
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‎projects/coremark/README.md‎

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# Coremark build script for ch32fun
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This allows you to easily build and run [Coremark](https://www.eembc.org/coremark/index.php) benchmark on any MCU that is supported in ch32fun. Coremark is industry adopted benchmark for roughly comparing core performance of different MCUs and other embedded processors. Same as all other benchmarks it can't be used to absolutely measure the performance of the device, but nevertheless it can be a useful tool when comparing and choosing among many different chip models available on the market. Also running this test with different compilers and/or compiler settings can show what is influencing the performance of your chip and how, and maybe it can help you to optimize your code if needed.
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If you want so compare your results with other known runs you can visit this page: https://www.eembc.org/coremark/scores.php
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Also there is an official result list for various WCH MCUs: https://special.wch.cn/zh_cn/coremark_scores/#/
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There were some doubts in legitimacy of those numbers, but after my own tests they seem pretty close to what I was getting on these chips, albeit the benchmark was compiled with pretty aggressive gcc flags, that you would rarely see in everyday life.
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## How to use
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- You will need a copy of [Coremark](https://github.com/eembc/coremark) in the ``coremark`` subfolder. Alternatively, you can point to the Coremark in some other location on your PC by editing ``COREMARK`` variable in the ``Makefile``.
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- Select your MCU model in the ``Makefile``
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- Connect your board to the PC and do ``make`` in this folder.
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- Open the terminal in minichlink, or do ``make terminal``, wait until the test is done running and results are printed.
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## Quirks and optimizations
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As stated in Coremark description for a result to be valid the benchmark needs run for at least 10 seconds. The duration of the test depends on the number of iterations. By default it is set to 4000, but it is too much for slower processors. You may want to decrease this number to 1500 or even 500. Why does it matter? This *port* uses a raw SysTick value to measure the time spent and if you are running SysTick at HCLK and the processor has a 32 bit counter, it will likely overflow and wrap around for longer durations of the test, this will inevitably produce a wrong result. So you would want a number of iterations be such that it takes 10-20 seconds to complete. You can easily change the number of iterations by editing ``CORE_ITERATIONS`` variable in the ``Makefile``.
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Another setting you can change (but shouldn't if you want a comparable result) is ``CORE_DATA_SIZE``. By default it is 2000 and it will use this much bytes in the RAM for a data buffer. This is why you can't run this benchmark on chips like ch32v003 or ch32v002 to get a number to compare with other known results.
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``CORE_MEM_METHOD`` is a setting that allows you to choose where the data is stored. The options are: Static - 0, Heap - 1 and Stack - 2. Most results online I've seen were using the Stack option.
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``OPT_FLAGS`` - gcc flags for optimizing the compilation of Coremark files. Usually they are compiled with ``-O3``. WCH used ``-Ofast -funroll-all-loops -finline-limit=600 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling -fno-code-hoisting`` for their official table. Some of these flags may even decrease the performance on some chips, you'll have to experiment with them. ``-funroll-all-loops`` - doubles the resulting binary and the size will depend on a number of iterations. The default compiler settings used in ch32fun are ``-Os -flto -ffunction-sections -fdata-sections -fmessage-length=0 -msmall-data-limit=8`` you can use them to see how much performance is traded for space optimization.
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The ``printf`` function that is used in ch32fun lacks float support, but to see the Coremark results you need it. This is why there is a third-party printf library in this folder.
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## Running from RAM
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Many WCH's chips have a rather slow flash memory. This impacts the performance drastically in some cases. The most advanced chips like ch32v20x and ch32v30x use a SRAM cache for the *zero-wait flash* to increase their performance, but chips from ch5xx family doesn't have that cache even though they have pretty fast cores. To measure the core performance on such chips you may want to runt the benchmark in the RAM. You can do it by using the ``make runfromram`` command. But be aware that you would need the resulting firmware size + data buffer be lower than the RAM size of your MCU. You can achieve this by changing compiler flags and disabling third-party printf library. If you disable printf lib, the results will print total number of ticks and you will have to calculate the result by yourself, but this is a worthy tradeoff.
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## Some results
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| |Marks |Flash/RAM|Frequency|Iterations|Compiler version|Build flags|
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|:- |:-: |:-: |:-: |:-: |:-: |:-: |
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|CH570 |27 |Flash |50MHz |500 |gcc 13.2.0 |-O3 |
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|CH570 |187 |RAM |100MHz |2500 |gcc 13.2.0 |-Os -flto -ffunction-sections -fdata-sections -fmessage-length=0 -msmall-data-limit=8 |
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|CH32V006|57 |Flash |48MHz |1500 |gcc 13.2.0 |-O3 |
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|CH32V006|40 |Flash |48MHz |1500 |gcc 13.2.0 |-Os -flto -ffunction-sections -fdata-sections -fmessage-length=0 -msmall-data-limit=8 |
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|CH32V006|62 |Flash |48MHz |1500 |gcc 13.2.0 |-O3 -funroll-all-loops -finline-limit=600 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling -fno-code-hoisting |
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|CH32X035|29 |Flash |48MHz |500 |gcc 13.2.0 |-Os -flto -ffunction-sections -fdata-sections -fmessage-length=0 -msmall-data-limit=8 |
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|CH32X035|71 |RAM |48MHz |1500 |gcc 13.2.0 |-Os -flto -ffunction-sections -fdata-sections -fmessage-length=0 -msmall-data-limit=8 |
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|CH32X035|106 |RAM |48MHz |1500 |gcc 13.2.0 |-O3 |
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|CH32X035|115 |RAM |48MHz |1500 |gcc 13.2.0 |-O3 -finline-limit=600 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling -fno-code-hoisting |
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|CH585 |242 |RAM |78MHz |4000 |gcc 13.2.0 |-O3 -funroll-all-loops -finline-limit=600 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling -fno-code-hoisting |
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|CH32V307|266 |Flash (zero-wait) |144MHz |4000 |gcc 13.2.0 |-Os -flto -ffunction-sections -fdata-sections -fmessage-length=0 -msmall-data-limit=8 |
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|CH32V307|384 |Flash (zero-wait) |144MHz |4000 |gcc 13.2.0 |-O3 |
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|CH32V307|459 |Flash (zero-wait) |144MHz |5000 |gcc 13.2.0 |-O3 -funroll-all-loops -finline-limit=600 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling -fno-code-hoisting|
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|CH32V307|463 |Flash (zero-wait) |144MHz |5000 |gcc 13.2.0 |-O3 -funroll-all-loops -finline-limit=600 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling |
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|CH32V307|469 |Flash (zero-wait) |144MHz |5000 |gcc 13.2.0 |-Ofast -funroll-all-loops -finline-limit=600 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling -fno-code-hoisting |
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I've included multiple ch32v307 results to demonstrate how unintuitively some compiler flags can influence the performance. Adding ``-fno-code-hoisting`` produced worse results with ``-O3`` than on all other chips I've tried, but with ``-Ofast`` it make result better.

‎projects/coremark/app_in_ram.ld‎

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ENTRY( InterruptVector )
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/* Run from RAM example, small RAM footprint so should run on any CH32V's */
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MEMORY
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{
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#if TARGET_MCU_LD == 0 /* v003 */
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2K
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#elif TARGET_MCU_LD == 1 /* v10x */
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#if MCU_PACKAGE == 1
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
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#elif MCU_PACKAGE == 2
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
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#else
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#error "Unknown MCU package"
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#endif
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#elif TARGET_MCU_LD == 2 /* v20x */
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#if MCU_PACKAGE == 1
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
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#elif MCU_PACKAGE == 2
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
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#elif MCU_PACKAGE == 3
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
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#else
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#error "Unknown MCU package"
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#endif
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#elif TARGET_MCU_LD == 3 /* v30x */
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#if MCU_PACKAGE == 1
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#if TARGET_MCU_MEMORY_SPLIT == 1
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
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#elif TARGET_MCU_MEMORY_SPLIT == 2
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
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#elif TARGET_MCU_MEMORY_SPLIT == 3
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
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#else
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
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#endif
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#elif MCU_PACKAGE == 2
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
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#else
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#error "Unknown MCU package"
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#endif
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#elif TARGET_MCU_LD == 4 /* x03x */
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#if MCU_PACKAGE == 1
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
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#else
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#error "Unknown MCU package"
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#endif
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#elif TARGET_MCU_LD == 5
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/* CH32V002 */
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 4K
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#elif TARGET_MCU_LD == 6
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/* CH32V005, CH32V004 */
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 6K
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#elif TARGET_MCU_LD == 7
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/* CH32V006, CH32V007 */
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K
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#elif TARGET_MCU_LD == 8
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/* CH582/3/4/5 */
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#if MCU_PACKAGE == 2 || MCU_PACKAGE == 3
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
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#elif MCU_PACKAGE == 4
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
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#elif MCU_PACKAGE == 5
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
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#else
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#error "Unknown MCU package"
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#endif
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#elif TARGET_MCU_LD == 9
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/* CH591/2 */
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#if MCU_PACKAGE == 1
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 26K
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#elif MCU_PACKAGE == 2
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 26K
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#else
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#error "Unknown MCU package"
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#endif
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#elif TARGET_MCU_LD == 10
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/* CH57x */
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#if MCU_PACKAGE == 0 || MCU_PACKAGE == 2
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 12K
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#elif MCU_PACKAGE == 1
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RAM (xrw) : ORIGIN = 0x20003800, LENGTH = 18K
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#elif MCU_PACKAGE == 3
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RAM (xrw) : ORIGIN = 0x20003800, LENGTH = 18K
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#else
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#error "Unknown MCU package"
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#endif
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#elif TARGET_MCU_LD == 11
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/* CH32H41x */
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#if MCU_PACKAGE == 1 || MCU_PACKAGE == 3
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RAM (xrw) : ORIGIN = 0x20100000, LENGTH = 512K
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#elif MCU_PACKAGE == 2
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RAM (xrw) : ORIGIN = 0x20100000, LENGTH = 512K
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#else
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#error "Unknown MCU package"
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#endif
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#else
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#error "Unknown MCU target"
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#endif
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}
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SECTIONS
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{
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.init :
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{
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_sinit = .;
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. = ALIGN(4);
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KEEP(*(SORT_NONE(.init)))
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. = ALIGN(4);
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_einit = .;
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} >RAM AT>RAM
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#if TARGET_MCU_LD == 8 || TARGET_MCU_LD == 9 || TARGET_MCU_LD == 10
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.highcodelalign :
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{
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. = ALIGN(4);
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PROVIDE(_highcode_lma = .);
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} >RAM AT>RAM
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.highcode :
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{
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. = ALIGN(4);
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PROVIDE(_highcode_vma_start = .);
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*(.highcode*)
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. = ALIGN(4);
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PROVIDE(_highcode_vma_end = .);
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} >RAM AT>RAM
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.data :
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{
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. = ALIGN(4);
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__global_pointer$ = . + 0x7f8;
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*(.gnu.linkonce.r.*)
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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. = ALIGN(4);
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*(.sdata .sdata.*)
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*(.sdata2*)
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*(.gnu.linkonce.s.*)
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. = ALIGN(4);
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*(.srodata.cst16)
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*(.srodata.cst8)
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*(.srodata.cst4)
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*(.srodata.cst2)
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*(.srodata .srodata.*)
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. = ALIGN(4);
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PROVIDE( _edata = .);
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} >RAM AT>RAM
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#endif
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.text :
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{
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. = ALIGN(4);
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*(.text)
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*(.text.*)
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*(.rodata)
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*(.rodata*)
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*(.gnu.linkonce.t.*)
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. = ALIGN(4);
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} >RAM AT>RAM
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.fini :
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{
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KEEP(*(SORT_NONE(.fini)))
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. = ALIGN(4);
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} >RAM AT>RAM
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PROVIDE( _etext = . );
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PROVIDE( _eitcm = . );
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.preinit_array :
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{
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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} >RAM AT>RAM
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.init_array :
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{
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
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KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
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PROVIDE_HIDDEN (__init_array_end = .);
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} >RAM AT>RAM
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.fini_array :
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{
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
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KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
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PROVIDE_HIDDEN (__fini_array_end = .);
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} >RAM AT>RAM
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.ctors :
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{
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/* gcc uses crtbegin.o to find the start of
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the constructors, so we make sure it is
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first. Because this is a wildcard, it
200+
doesn't matter if the user does not
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actually link against crtbegin.o; the
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linker won't look for a file to match a
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wildcard. The wildcard also means that it
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doesn't matter which directory crtbegin.o
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is in. */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*crtbegin?.o(.ctors))
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/* We don't want to include the .ctor section from
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the crtend.o file until after the sorted ctors.
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The .ctor section from the crtend file contains the
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end of ctors marker and it must be last */
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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} >RAM AT>RAM
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.dtors :
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{
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KEEP (*crtbegin.o(.dtors))
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KEEP (*crtbegin?.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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} >RAM AT>RAM
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.dalign :
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{
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. = ALIGN(4);
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PROVIDE(_data_vma = .);
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} >RAM AT>RAM
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.dlalign :
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{
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. = ALIGN(4);
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PROVIDE(_data_lma = .);
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} >RAM AT>RAM
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#if TARGET_MCU_LD != 8 && TARGET_MCU_LD != 9 && TARGET_MCU_LD != 10
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.data :
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{
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. = ALIGN(4);
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__global_pointer$ = . + 0x7f8;
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*(.gnu.linkonce.r.*)
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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. = ALIGN(4);
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*(.sdata .sdata.*)
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*(.sdata2*)
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*(.gnu.linkonce.s.*)
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. = ALIGN(4);
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*(.srodata.cst16)
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*(.srodata.cst8)
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*(.srodata.cst4)
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*(.srodata.cst2)
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*(.srodata .srodata.*)
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. = ALIGN(4);
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PROVIDE( _edata = .);
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} >RAM AT>RAM
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#endif
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.bss :
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{
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. = ALIGN(4);
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PROVIDE( _sbss = .);
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*(.sbss*)
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*(.gnu.linkonce.sb.*)
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*(.bss*)
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*(.gnu.linkonce.b.*)
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*(COMMON*)
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. = ALIGN(4);
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PROVIDE( _ebss = .);
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} >RAM AT>RAM
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PROVIDE( _end = _ebss);
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PROVIDE( end = . );
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PROVIDE( _eusrstack = ORIGIN(RAM) + LENGTH(RAM));
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}
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