CH32V3xx/CH32V20x flash size configuration issues

[Kirizu-Official]

When I was using ch32v208cbu6, I noticed that the flash size in b was only configured to 128KKB, But actually there is 480KB max for Code FLASH.

CH32V208 has "zero-wait run area" and "non-zero-wait area":

• "non-zero-wait area"
  slow flash area, used for user application and constant data storage, and also store SNV of ble.
• "zero-wait run area"
  fast flash area, used for cpu.

After the chip is reset, the hardware copies the code from the slow flash to the fast flash area, and then runs it from the fast flash.
The size of the flash shown on the wch website is zero-wait run area".

And mentioned there has 480K flash for user code in datasheet.

Because usually 32kb is allocated for the SRAM (128K ROM + 64K RAM), so the code flash area is usually configured to 448K. This is also the default configuration in Link.ld. (480k for user code when select 160K ROM + 32K RAM)

MEMORY
{  
/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */
/*
	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
*/ 

/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
/*
	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
*/ 
  
/* CH32V20x_D8 - CH32V203RB
   CH32V20x_D8W - CH32V208x
   FLASH + RAM supports the following configuration
   FLASH-128K + RAM-64K
   FLASH-144K + RAM-48K
   FLASH-160K + RAM-32K
*/
	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 448K
	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K

}