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| 1 | +2025-09-24 Dusan Stojkovic <Dusan.Stojkovic@rt-rk.com> |
| 2 | + |
| 3 | + PR target/121778 |
| 4 | + * config/riscv/riscv.md: Add define_split pattern. |
| 5 | + |
| 6 | +2025-09-24 Andrew Pinski <andrew.pinski@oss.qualcomm.com> |
| 7 | + |
| 8 | + PR tree-optimization/121762 |
| 9 | + * gimple-fold.cc (gimple_fold_builtin_assume_aligned): New function. |
| 10 | + (gimple_fold_builtin): Call gimple_fold_builtin_assume_aligned |
| 11 | + for BUILT_IN_ASSUME_ALIGNED. |
| 12 | + * tree-ssa-ccp.cc (pass_fold_builtins::execute): Remove handling |
| 13 | + of BUILT_IN_ASSUME_ALIGNED. |
| 14 | + |
| 15 | +2025-09-24 Jennifer Schmitz <jschmitz@nvidia.com> |
| 16 | + |
| 17 | + * config/aarch64/aarch64.md: Include neoversev2.md. |
| 18 | + * config/aarch64/tuning_models/neoversev2.h: Enable dispatch |
| 19 | + scheduling and add dispatch constraints. |
| 20 | + * config/aarch64/neoversev2.md: New file and new instruction attribute |
| 21 | + neoversev2_dispatch. |
| 22 | + |
| 23 | +2025-09-24 Jennifer Schmitz <jschmitz@nvidia.com> |
| 24 | + |
| 25 | + * config.gcc: Add aarch64-sched-dispatch.o to extra_objs. |
| 26 | + * config/aarch64/aarch64-protos.h (struct tune_params): New |
| 27 | + field for dispatch scheduling. |
| 28 | + (struct dispatch_constraint_info): New struct for dispatch scheduling. |
| 29 | + * config/aarch64/aarch64-tuning-flags.def |
| 30 | + (AARCH64_EXTRA_TUNING_OPTION): New flag to enable dispatch scheduling. |
| 31 | + * config/aarch64/aarch64.cc (TARGET_SCHED_DISPATCH): Implement |
| 32 | + target hook. |
| 33 | + (TARGET_SCHED_DISPATCH_DO): Likewise. |
| 34 | + (aarch64_override_options_internal): Add check for definition of |
| 35 | + dispatch constraints if dispatch-scheduling tune flag is set. |
| 36 | + * config/aarch64/t-aarch64: Add aarch64-sched-dispatch.o. |
| 37 | + * config/aarch64/tuning_models/a64fx.h: Initialize fields for |
| 38 | + dispatch scheduling in tune_params. |
| 39 | + * config/aarch64/tuning_models/ampere1.h: Likewise. |
| 40 | + * config/aarch64/tuning_models/ampere1a.h: Likewise. |
| 41 | + * config/aarch64/tuning_models/ampere1b.h: Likewise. |
| 42 | + * config/aarch64/tuning_models/cortexa35.h: Likewise. |
| 43 | + * config/aarch64/tuning_models/cortexa53.h: Likewise. |
| 44 | + * config/aarch64/tuning_models/cortexa57.h: Likewise. |
| 45 | + * config/aarch64/tuning_models/cortexa72.h: Likewise. |
| 46 | + * config/aarch64/tuning_models/cortexa73.h: Likewise. |
| 47 | + * config/aarch64/tuning_models/cortexx925.h: Likewise. |
| 48 | + * config/aarch64/tuning_models/emag.h: Likewise. |
| 49 | + * config/aarch64/tuning_models/exynosm1.h: Likewise. |
| 50 | + * config/aarch64/tuning_models/fujitsu_monaka.h: Likewise. |
| 51 | + * config/aarch64/tuning_models/generic.h: Likewise. |
| 52 | + * config/aarch64/tuning_models/generic_armv8_a.h: Likewise. |
| 53 | + * config/aarch64/tuning_models/generic_armv9_a.h: Likewise. |
| 54 | + * config/aarch64/tuning_models/neoverse512tvb.h: Likewise. |
| 55 | + * config/aarch64/tuning_models/neoversen1.h: Likewise. |
| 56 | + * config/aarch64/tuning_models/neoversen2.h: Likewise. |
| 57 | + * config/aarch64/tuning_models/neoversen3.h: Likewise. |
| 58 | + * config/aarch64/tuning_models/neoversev1.h: Likewise. |
| 59 | + * config/aarch64/tuning_models/neoversev2.h: Likewise. |
| 60 | + * config/aarch64/tuning_models/neoversev3.h: Likewise. |
| 61 | + * config/aarch64/tuning_models/neoversev3ae.h: Likewise. |
| 62 | + * config/aarch64/tuning_models/olympus.h: Likewise. |
| 63 | + * config/aarch64/tuning_models/qdf24xx.h: Likewise. |
| 64 | + * config/aarch64/tuning_models/saphira.h: Likewise. |
| 65 | + * config/aarch64/tuning_models/thunderx.h: Likewise. |
| 66 | + * config/aarch64/tuning_models/thunderx2t99.h: Likewise. |
| 67 | + * config/aarch64/tuning_models/thunderx3t110.h: Likewise. |
| 68 | + * config/aarch64/tuning_models/thunderxt88.h: Likewise. |
| 69 | + * config/aarch64/tuning_models/tsv110.h: Likewise. |
| 70 | + * config/aarch64/tuning_models/xgene1.h: Likewise. |
| 71 | + * config/aarch64/aarch64-sched-dispatch.cc: New file for |
| 72 | + dispatch scheduling for aarch64. |
| 73 | + * config/aarch64/aarch64-sched-dispatch.h: New header file. |
| 74 | + |
| 75 | +2025-09-24 Jennifer Schmitz <jschmitz@nvidia.com> |
| 76 | + |
| 77 | + * config/aarch64/aarch64-sve.md: Annotate instructions with |
| 78 | + attribute sve_type. |
| 79 | + * config/aarch64/aarch64-sve2.md: Likewise. |
| 80 | + * config/aarch64/aarch64.md (sve_type): New attribute sve_type. |
| 81 | + * config/aarch64/iterators.md (sve_type_unspec): New int attribute. |
| 82 | + (sve_type_int): New code attribute. |
| 83 | + (sve_type_fp): New int attribute. |
| 84 | + |
| 85 | +2025-09-24 Richard Biener <rguenther@suse.de> |
| 86 | + |
| 87 | + PR tree-optimization/116816 |
| 88 | + * tree-vect-stmts.cc (get_load_store_type): Allow multi-lane |
| 89 | + single-element interleaving to fall back to VMAT_ELEMENTWISE. |
| 90 | + Fall back to VMAT_ELEMENTWISE when we cannot handle a load |
| 91 | + permutation. |
| 92 | + (vectorizable_load): Do not check a load permutation |
| 93 | + for VMAT_ELEMENTWISE. Handle grouped loads with |
| 94 | + VMAT_ELEMENTWISE and directly apply a load permutation. |
| 95 | + |
| 96 | +2025-09-24 Richard Biener <rguenther@suse.de> |
| 97 | + |
| 98 | + * tree-vect-stmts.cc (get_load_store_type): Explicitly fail |
| 99 | + when we end up with VMAT_ELEMENTWISE for BB vectorization. |
| 100 | + |
| 101 | +2025-09-24 Xi Ruoyao <xry111@xry111.site> |
| 102 | + |
| 103 | + PR tree-optimization/122040 |
| 104 | + * doc/invoke.texi (-fisolate-erroneous-paths-dereference): |
| 105 | + Mention it also turns division by zero into a trap in addition |
| 106 | + to null dereference. |
| 107 | + |
| 108 | +2025-09-24 Xi Ruoyao <xry111@xry111.site> |
| 109 | + |
| 110 | + PR middle-end/66462 |
| 111 | + * config/loongarch/loongarch.md (FCLASS_MASK): Add 3. |
| 112 | + (fclass_optab): Assign isnan for 3. |
| 113 | + (<FCLASS_MASK:fclass_optab><ANYF:mode>2): If FCLASS_MASK is 3, |
| 114 | + only enable when -fsignaling-nans. |
| 115 | + |
| 116 | +2025-09-24 Pan Li <pan2.li@intel.com> |
| 117 | + |
| 118 | + * match.pd: Add pattern of mult and reuse the widen-mul |
| 119 | + by for keyword. |
| 120 | + |
1 | 121 | 2025-09-23 David Malcolm <dmalcolm@redhat.com> |
2 | 122 |
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3 | 123 | PR diagnostics/121986 |
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