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iajbarDebadri Basak
iajbar
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Debadri Basak
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[Hexagon] Add V81 instructions and intrinsics (llvm#165903)
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‎clang/lib/Headers/hvx_hexagon_protos.h‎

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Original file line numberDiff line numberDiff line change
@@ -5605,6 +5605,399 @@
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__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_f8)(Vu, Vv)
56065606
#endif /* __HEXAGON_ARCH___ >= 79 */
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5608+
#if __HVX_ARCH__ >= 81
5609+
/* ==========================================================================
5610+
Assembly Syntax: Vd32.qf16=vabs(Vu32.hf)
5611+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vhf(HVX_Vector Vu)
5612+
Instruction Type: CVI_VS
5613+
Execution Slots: SLOT0123
5614+
========================================================================== */
5615+
5616+
#define Q6_Vqf16_vabs_Vhf(Vu) \
5617+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_hf)(Vu)
5618+
#endif /* __HEXAGON_ARCH___ >= 81 */
5619+
5620+
#if __HVX_ARCH__ >= 81
5621+
/* ==========================================================================
5622+
Assembly Syntax: Vd32.qf16=vabs(Vu32.qf16)
5623+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vqf16(HVX_Vector Vu)
5624+
Instruction Type: CVI_VS
5625+
Execution Slots: SLOT0123
5626+
========================================================================== */
5627+
5628+
#define Q6_Vqf16_vabs_Vqf16(Vu) \
5629+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_qf16)(Vu)
5630+
#endif /* __HEXAGON_ARCH___ >= 81 */
5631+
5632+
#if __HVX_ARCH__ >= 81
5633+
/* ==========================================================================
5634+
Assembly Syntax: Vd32.qf32=vabs(Vu32.qf32)
5635+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vqf32(HVX_Vector Vu)
5636+
Instruction Type: CVI_VS
5637+
Execution Slots: SLOT0123
5638+
========================================================================== */
5639+
5640+
#define Q6_Vqf32_vabs_Vqf32(Vu) \
5641+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_qf32)(Vu)
5642+
#endif /* __HEXAGON_ARCH___ >= 81 */
5643+
5644+
#if __HVX_ARCH__ >= 81
5645+
/* ==========================================================================
5646+
Assembly Syntax: Vd32.qf32=vabs(Vu32.sf)
5647+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vsf(HVX_Vector Vu)
5648+
Instruction Type: CVI_VS
5649+
Execution Slots: SLOT0123
5650+
========================================================================== */
5651+
5652+
#define Q6_Vqf32_vabs_Vsf(Vu) \
5653+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_sf)(Vu)
5654+
#endif /* __HEXAGON_ARCH___ >= 81 */
5655+
5656+
#if __HVX_ARCH__ >= 81
5657+
/* ==========================================================================
5658+
Assembly Syntax: Vd32=valign4(Vu32,Vv32,Rt8)
5659+
C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector
5660+
Vv, Word32 Rt) Instruction Type: CVI_VA Execution Slots: SLOT0123
5661+
========================================================================== */
5662+
5663+
#define Q6_V_valign4_VVR(Vu, Vv, Rt) \
5664+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valign4)(Vu, Vv, Rt)
5665+
#endif /* __HEXAGON_ARCH___ >= 81 */
5666+
5667+
#if __HVX_ARCH__ >= 81
5668+
/* ==========================================================================
5669+
Assembly Syntax: Vd32.bf=Vuu32.qf32
5670+
C Intrinsic Prototype: HVX_Vector Q6_Vbf_equals_Wqf32(HVX_VectorPair Vuu)
5671+
Instruction Type: CVI_VS
5672+
Execution Slots: SLOT0123
5673+
========================================================================== */
5674+
5675+
#define Q6_Vbf_equals_Wqf32(Vuu) \
5676+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_bf_qf32)(Vuu)
5677+
#endif /* __HEXAGON_ARCH___ >= 81 */
5678+
5679+
#if __HVX_ARCH__ >= 81
5680+
/* ==========================================================================
5681+
Assembly Syntax: Vd32.f8=Vu32.qf16
5682+
C Intrinsic Prototype: HVX_Vector Q6_V_equals_Vqf16(HVX_Vector Vu)
5683+
Instruction Type: CVI_VS
5684+
Execution Slots: SLOT0123
5685+
========================================================================== */
5686+
5687+
#define Q6_V_equals_Vqf16(Vu) \
5688+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_f8_qf16)(Vu)
5689+
#endif /* __HEXAGON_ARCH___ >= 81 */
5690+
5691+
#if __HVX_ARCH__ >= 81
5692+
/* ==========================================================================
5693+
Assembly Syntax: Vd32.h=Vu32.hf:rnd
5694+
C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf_rnd(HVX_Vector Vu)
5695+
Instruction Type: CVI_VS
5696+
Execution Slots: SLOT0123
5697+
========================================================================== */
5698+
5699+
#define Q6_Vh_equals_Vhf_rnd(Vu) \
5700+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf_rnd)(Vu)
5701+
#endif /* __HEXAGON_ARCH___ >= 81 */
5702+
5703+
#if __HVX_ARCH__ >= 81
5704+
/* ==========================================================================
5705+
Assembly Syntax: Vdd32.qf16=Vu32.f8
5706+
C Intrinsic Prototype: HVX_VectorPair Q6_Wqf16_equals_V(HVX_Vector Vu)
5707+
Instruction Type: CVI_VP_VS
5708+
Execution Slots: SLOT0123
5709+
========================================================================== */
5710+
5711+
#define Q6_Wqf16_equals_V(Vu) \
5712+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_f8)(Vu)
5713+
#endif /* __HEXAGON_ARCH___ >= 81 */
5714+
5715+
#if __HVX_ARCH__ >= 81
5716+
/* ==========================================================================
5717+
Assembly Syntax: Vd32.qf16=Vu32.hf
5718+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vhf(HVX_Vector Vu)
5719+
Instruction Type: CVI_VS
5720+
Execution Slots: SLOT0123
5721+
========================================================================== */
5722+
5723+
#define Q6_Vqf16_equals_Vhf(Vu) \
5724+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_hf)(Vu)
5725+
#endif /* __HEXAGON_ARCH___ >= 81 */
5726+
5727+
#if __HVX_ARCH__ >= 81
5728+
/* ==========================================================================
5729+
Assembly Syntax: Vd32.qf16=Vu32.qf16
5730+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vqf16(HVX_Vector Vu)
5731+
Instruction Type: CVI_VS
5732+
Execution Slots: SLOT0123
5733+
========================================================================== */
5734+
5735+
#define Q6_Vqf16_equals_Vqf16(Vu) \
5736+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_qf16)(Vu)
5737+
#endif /* __HEXAGON_ARCH___ >= 81 */
5738+
5739+
#if __HVX_ARCH__ >= 81
5740+
/* ==========================================================================
5741+
Assembly Syntax: Vd32.qf32=Vu32.qf32
5742+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vqf32(HVX_Vector Vu)
5743+
Instruction Type: CVI_VS
5744+
Execution Slots: SLOT0123
5745+
========================================================================== */
5746+
5747+
#define Q6_Vqf32_equals_Vqf32(Vu) \
5748+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_qf32)(Vu)
5749+
#endif /* __HEXAGON_ARCH___ >= 81 */
5750+
5751+
#if __HVX_ARCH__ >= 81
5752+
/* ==========================================================================
5753+
Assembly Syntax: Vd32.qf32=Vu32.sf
5754+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vsf(HVX_Vector Vu)
5755+
Instruction Type: CVI_VS
5756+
Execution Slots: SLOT0123
5757+
========================================================================== */
5758+
5759+
#define Q6_Vqf32_equals_Vsf(Vu) \
5760+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_sf)(Vu)
5761+
#endif /* __HEXAGON_ARCH___ >= 81 */
5762+
5763+
#if __HVX_ARCH__ >= 81
5764+
/* ==========================================================================
5765+
Assembly Syntax: Qd4=vcmp.eq(Vu32.hf,Vv32.hf)
5766+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu,
5767+
HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123
5768+
========================================================================== */
5769+
5770+
#define Q6_Q_vcmp_eq_VhfVhf(Vu, Vv) \
5771+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
5772+
(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf)(Vu, Vv)), -1)
5773+
#endif /* __HEXAGON_ARCH___ >= 81 */
5774+
5775+
#if __HVX_ARCH__ >= 81
5776+
/* ==========================================================================
5777+
Assembly Syntax: Qx4&=vcmp.eq(Vu32.hf,Vv32.hf)
5778+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred
5779+
Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
5780+
Slots: SLOT0123
5781+
========================================================================== */
5782+
5783+
#define Q6_Q_vcmp_eqand_QVhfVhf(Qx, Vu, Vv) \
5784+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
5785+
(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_and)( \
5786+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \
5787+
Vv)), \
5788+
-1)
5789+
#endif /* __HEXAGON_ARCH___ >= 81 */
5790+
5791+
#if __HVX_ARCH__ >= 81
5792+
/* ==========================================================================
5793+
Assembly Syntax: Qx4|=vcmp.eq(Vu32.hf,Vv32.hf)
5794+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred
5795+
Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
5796+
Slots: SLOT0123
5797+
========================================================================== */
5798+
5799+
#define Q6_Q_vcmp_eqor_QVhfVhf(Qx, Vu, Vv) \
5800+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
5801+
(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_or)( \
5802+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \
5803+
Vv)), \
5804+
-1)
5805+
#endif /* __HEXAGON_ARCH___ >= 81 */
5806+
5807+
#if __HVX_ARCH__ >= 81
5808+
/* ==========================================================================
5809+
Assembly Syntax: Qx4^=vcmp.eq(Vu32.hf,Vv32.hf)
5810+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred
5811+
Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
5812+
Slots: SLOT0123
5813+
========================================================================== */
5814+
5815+
#define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx, Vu, Vv) \
5816+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
5817+
(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_xor)( \
5818+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \
5819+
Vv)), \
5820+
-1)
5821+
#endif /* __HEXAGON_ARCH___ >= 81 */
5822+
5823+
#if __HVX_ARCH__ >= 81
5824+
/* ==========================================================================
5825+
Assembly Syntax: Qd4=vcmp.eq(Vu32.sf,Vv32.sf)
5826+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu,
5827+
HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123
5828+
========================================================================== */
5829+
5830+
#define Q6_Q_vcmp_eq_VsfVsf(Vu, Vv) \
5831+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
5832+
(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf)(Vu, Vv)), -1)
5833+
#endif /* __HEXAGON_ARCH___ >= 81 */
5834+
5835+
#if __HVX_ARCH__ >= 81
5836+
/* ==========================================================================
5837+
Assembly Syntax: Qx4&=vcmp.eq(Vu32.sf,Vv32.sf)
5838+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred
5839+
Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
5840+
Slots: SLOT0123
5841+
========================================================================== */
5842+
5843+
#define Q6_Q_vcmp_eqand_QVsfVsf(Qx, Vu, Vv) \
5844+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
5845+
(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_and)( \
5846+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \
5847+
Vv)), \
5848+
-1)
5849+
#endif /* __HEXAGON_ARCH___ >= 81 */
5850+
5851+
#if __HVX_ARCH__ >= 81
5852+
/* ==========================================================================
5853+
Assembly Syntax: Qx4|=vcmp.eq(Vu32.sf,Vv32.sf)
5854+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred
5855+
Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
5856+
Slots: SLOT0123
5857+
========================================================================== */
5858+
5859+
#define Q6_Q_vcmp_eqor_QVsfVsf(Qx, Vu, Vv) \
5860+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
5861+
(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_or)( \
5862+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \
5863+
Vv)), \
5864+
-1)
5865+
#endif /* __HEXAGON_ARCH___ >= 81 */
5866+
5867+
#if __HVX_ARCH__ >= 81
5868+
/* ==========================================================================
5869+
Assembly Syntax: Qx4^=vcmp.eq(Vu32.sf,Vv32.sf)
5870+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred
5871+
Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
5872+
Slots: SLOT0123
5873+
========================================================================== */
5874+
5875+
#define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx, Vu, Vv) \
5876+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
5877+
(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_xor)( \
5878+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \
5879+
Vv)), \
5880+
-1)
5881+
#endif /* __HEXAGON_ARCH___ >= 81 */
5882+
5883+
#if __HVX_ARCH__ >= 81
5884+
/* ==========================================================================
5885+
Assembly Syntax: Vd32.w=vilog2(Vu32.hf)
5886+
C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vhf(HVX_Vector Vu)
5887+
Instruction Type: CVI_VS
5888+
Execution Slots: SLOT0123
5889+
========================================================================== */
5890+
5891+
#define Q6_Vw_vilog2_Vhf(Vu) \
5892+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_hf)(Vu)
5893+
#endif /* __HEXAGON_ARCH___ >= 81 */
5894+
5895+
#if __HVX_ARCH__ >= 81
5896+
/* ==========================================================================
5897+
Assembly Syntax: Vd32.w=vilog2(Vu32.qf16)
5898+
C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf16(HVX_Vector Vu)
5899+
Instruction Type: CVI_VS
5900+
Execution Slots: SLOT0123
5901+
========================================================================== */
5902+
5903+
#define Q6_Vw_vilog2_Vqf16(Vu) \
5904+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf16)(Vu)
5905+
#endif /* __HEXAGON_ARCH___ >= 81 */
5906+
5907+
#if __HVX_ARCH__ >= 81
5908+
/* ==========================================================================
5909+
Assembly Syntax: Vd32.w=vilog2(Vu32.qf32)
5910+
C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf32(HVX_Vector Vu)
5911+
Instruction Type: CVI_VS
5912+
Execution Slots: SLOT0123
5913+
========================================================================== */
5914+
5915+
#define Q6_Vw_vilog2_Vqf32(Vu) \
5916+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf32)(Vu)
5917+
#endif /* __HEXAGON_ARCH___ >= 81 */
5918+
5919+
#if __HVX_ARCH__ >= 81
5920+
/* ==========================================================================
5921+
Assembly Syntax: Vd32.w=vilog2(Vu32.sf)
5922+
C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vsf(HVX_Vector Vu)
5923+
Instruction Type: CVI_VS
5924+
Execution Slots: SLOT0123
5925+
========================================================================== */
5926+
5927+
#define Q6_Vw_vilog2_Vsf(Vu) \
5928+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_sf)(Vu)
5929+
#endif /* __HEXAGON_ARCH___ >= 81 */
5930+
5931+
#if __HVX_ARCH__ >= 81
5932+
/* ==========================================================================
5933+
Assembly Syntax: Vd32.qf16=vneg(Vu32.hf)
5934+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vhf(HVX_Vector Vu)
5935+
Instruction Type: CVI_VS
5936+
Execution Slots: SLOT0123
5937+
========================================================================== */
5938+
5939+
#define Q6_Vqf16_vneg_Vhf(Vu) \
5940+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_hf)(Vu)
5941+
#endif /* __HEXAGON_ARCH___ >= 81 */
5942+
5943+
#if __HVX_ARCH__ >= 81
5944+
/* ==========================================================================
5945+
Assembly Syntax: Vd32.qf16=vneg(Vu32.qf16)
5946+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vqf16(HVX_Vector Vu)
5947+
Instruction Type: CVI_VS
5948+
Execution Slots: SLOT0123
5949+
========================================================================== */
5950+
5951+
#define Q6_Vqf16_vneg_Vqf16(Vu) \
5952+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_qf16)(Vu)
5953+
#endif /* __HEXAGON_ARCH___ >= 81 */
5954+
5955+
#if __HVX_ARCH__ >= 81
5956+
/* ==========================================================================
5957+
Assembly Syntax: Vd32.qf32=vneg(Vu32.qf32)
5958+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vqf32(HVX_Vector Vu)
5959+
Instruction Type: CVI_VS
5960+
Execution Slots: SLOT0123
5961+
========================================================================== */
5962+
5963+
#define Q6_Vqf32_vneg_Vqf32(Vu) \
5964+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_qf32)(Vu)
5965+
#endif /* __HEXAGON_ARCH___ >= 81 */
5966+
5967+
#if __HVX_ARCH__ >= 81
5968+
/* ==========================================================================
5969+
Assembly Syntax: Vd32.qf32=vneg(Vu32.sf)
5970+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vsf(HVX_Vector Vu)
5971+
Instruction Type: CVI_VS
5972+
Execution Slots: SLOT0123
5973+
========================================================================== */
5974+
5975+
#define Q6_Vqf32_vneg_Vsf(Vu) \
5976+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_sf)(Vu)
5977+
#endif /* __HEXAGON_ARCH___ >= 81 */
5978+
5979+
#if __HVX_ARCH__ >= 81
5980+
/* ==========================================================================
5981+
Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.qf16)
5982+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu,
5983+
HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123
5984+
========================================================================== */
5985+
5986+
#define Q6_Vqf16_vsub_VhfVqf16(Vu, Vv) \
5987+
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_mix)(Vu, Vv)
5988+
#endif /* __HEXAGON_ARCH___ >= 81 */
5989+
5990+
#if __HVX_ARCH__ >= 81
5991+
/* ==========================================================================
5992+
Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.qf32)
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C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu,
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HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123
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========================================================================== */
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#define Q6_Vqf32_vsub_VsfVqf32(Vu, Vv) \
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__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_mix)(Vu, Vv)
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#endif /* __HEXAGON_ARCH___ >= 81 */
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#endif /* __HVX__ */
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#endif

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