Further workaround for verilator/verilator#6893

Author: Oron Port

compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogTypePrinter.scala

@@ -56,12 +56,15 @@ protected trait VerilogTypePrinter extends AbstractTypePrinter:
       dfType.entries.view
         .map((n, v) => s"`${enumName}_${n}: $funcName = \"${enumName}_${n}\";")
         .mkString("\n").hindent(2)
+    // workaround for verilator bug: https://github.com/verilator/verilator/issues/6893
     s"""|function [8*${maxCharWidth}:1] $funcName;
+        |  /* verilator lint_off UNUSEDSIGNAL */
         |  input [${dfType.width - 1}:0] value;
         |  case (value)
         |${cases}
         |    default: $funcName = "?";
         |  endcase
+        |  /* verilator lint_on UNUSEDSIGNAL */
         |endfunction""".stripMargin
   end csDFEnumToStringFuncDcl
   def csDFEnumDcl(dfType: DFEnum, global: Boolean): String =

compiler/stages/src/test/scala/StagesSpec/PrintVerilogCodeSpec.scala

@@ -1163,13 +1163,15 @@ class PrintVerilogCodeSpec extends StageSpec:
          |  `define MyEnum_B 1
          |  `define MyEnum_C 2
          |  function [8*8:1] MyEnum_to_string;
+         |    /* verilator lint_off UNUSEDSIGNAL */
          |    input [1:0] value;
          |    case (value)
          |      `MyEnum_A: MyEnum_to_string = "MyEnum_A";
          |      `MyEnum_B: MyEnum_to_string = "MyEnum_B";
          |      `MyEnum_C: MyEnum_to_string = "MyEnum_C";
          |      default: MyEnum_to_string = "?";
          |    endcase
+         |    /* verilator lint_on UNUSEDSIGNAL */
          |  endfunction
          |  parameter bar = {param, "!"};
          |  parameter param2 = {2{param}};

lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v2001/hdl/ALU_defs.vh

@@ -17,6 +17,7 @@
 `define ALUSel_COPY1 10
 
 function [8*12:1] ALUSel_to_string;
+  /* verilator lint_off UNUSEDSIGNAL */
   input [3:0] value;
   case (value)
     `ALUSel_ADD: ALUSel_to_string = "ALUSel_ADD";
@@ -32,6 +33,7 @@ function [8*12:1] ALUSel_to_string;
     `ALUSel_COPY1: ALUSel_to_string = "ALUSel_COPY1";
     default: ALUSel_to_string = "?";
   endcase
+  /* verilator lint_on UNUSEDSIGNAL */
 endfunction
 `undef ALU_DEFS_MODULE
 `endif

lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v95/hdl/ALU_defs.vh

@@ -17,6 +17,7 @@
 `define ALUSel_COPY1 10
 
 function [8*12:1] ALUSel_to_string;
+  /* verilator lint_off UNUSEDSIGNAL */
   input [3:0] value;
   case (value)
     `ALUSel_ADD: ALUSel_to_string = "ALUSel_ADD";
@@ -32,6 +33,7 @@ function [8*12:1] ALUSel_to_string;
     `ALUSel_COPY1: ALUSel_to_string = "ALUSel_COPY1";
     default: ALUSel_to_string = "?";
   endcase
+  /* verilator lint_on UNUSEDSIGNAL */
 endfunction
 `undef ALU_DEFS_MODULE
 `endif

lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v2001/hdl/UART_Tx.v

@@ -23,6 +23,7 @@ module UART_Tx#(
   `define Status_StopBit 8
   `define Status_Finalize 16
   function [8*15:1] Status_to_string;
+    /* verilator lint_off UNUSEDSIGNAL */
     input [4:0] value;
     case (value)
       `Status_Idle: Status_to_string = "Status_Idle";
@@ -32,6 +33,7 @@ module UART_Tx#(
       `Status_Finalize: Status_to_string = "Status_Finalize";
       default: Status_to_string = "?";
     endcase
+    /* verilator lint_on UNUSEDSIGNAL */
   endfunction
   reg [4:0] status;
   reg [clog2(BIT_CLOCKS) - 1:0] bitClkCnt;

lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v95/hdl/UART_Tx.v

@@ -22,6 +22,7 @@ module UART_Tx(
   `define Status_StopBit 8
   `define Status_Finalize 16
   function [8*15:1] Status_to_string;
+    /* verilator lint_off UNUSEDSIGNAL */
     input [4:0] value;
     case (value)
       `Status_Idle: Status_to_string = "Status_Idle";
@@ -31,6 +32,7 @@ module UART_Tx(
       `Status_Finalize: Status_to_string = "Status_Finalize";
       default: Status_to_string = "?";
     endcase
+    /* verilator lint_on UNUSEDSIGNAL */
   endfunction
   input  wire   clk;
   input  wire   rst;

lib/src/test/resources/ref/docExamples.ugdemos.demo4.LRShiftFlatSpec/verilog.v2001/hdl/LRShiftFlat_defs.vh

@@ -8,12 +8,14 @@
 `define ShiftDir_Right 1
 
 function [8*14:1] ShiftDir_to_string;
+  /* verilator lint_off UNUSEDSIGNAL */
   input [0:0] value;
   case (value)
     `ShiftDir_Left: ShiftDir_to_string = "ShiftDir_Left";
     `ShiftDir_Right: ShiftDir_to_string = "ShiftDir_Right";
     default: ShiftDir_to_string = "?";
   endcase
+  /* verilator lint_on UNUSEDSIGNAL */
 endfunction
 `undef LRSHIFTFLAT_DEFS_MODULE
 `endif

lib/src/test/resources/ref/docExamples.ugdemos.demo4.LRShiftFlatSpec/verilog.v95/hdl/LRShiftFlat_defs.vh

@@ -8,12 +8,14 @@
 `define ShiftDir_Right 1
 
 function [8*14:1] ShiftDir_to_string;
+  /* verilator lint_off UNUSEDSIGNAL */
   input [0:0] value;
   case (value)
     `ShiftDir_Left: ShiftDir_to_string = "ShiftDir_Left";
     `ShiftDir_Right: ShiftDir_to_string = "ShiftDir_Right";
     default: ShiftDir_to_string = "?";
   endcase
+  /* verilator lint_on UNUSEDSIGNAL */
 endfunction
 `undef LRSHIFTFLAT_DEFS_MODULE
 `endif

lib/src/test/resources/ref/docExamples.ugdemos.demo5.LRShiftDirectSpec/verilog.v2001/hdl/LRShiftDirect_defs.vh

@@ -8,12 +8,14 @@
 `define ShiftDir_Right 1
 
 function [8*14:1] ShiftDir_to_string;
+  /* verilator lint_off UNUSEDSIGNAL */
   input [0:0] value;
   case (value)
     `ShiftDir_Left: ShiftDir_to_string = "ShiftDir_Left";
     `ShiftDir_Right: ShiftDir_to_string = "ShiftDir_Right";
     default: ShiftDir_to_string = "?";
   endcase
+  /* verilator lint_on UNUSEDSIGNAL */
 endfunction
 `undef LRSHIFTDIRECT_DEFS_MODULE
 `endif

lib/src/test/resources/ref/docExamples.ugdemos.demo5.LRShiftDirectSpec/verilog.v95/hdl/LRShiftDirect_defs.vh

@@ -8,12 +8,14 @@
 `define ShiftDir_Right 1
 
 function [8*14:1] ShiftDir_to_string;
+  /* verilator lint_off UNUSEDSIGNAL */
   input [0:0] value;
   case (value)
     `ShiftDir_Left: ShiftDir_to_string = "ShiftDir_Left";
     `ShiftDir_Right: ShiftDir_to_string = "ShiftDir_Right";
     default: ShiftDir_to_string = "?";
   endcase
+  /* verilator lint_on UNUSEDSIGNAL */
 endfunction
 `undef LRSHIFTDIRECT_DEFS_MODULE
 `endif