fix ToED sequential process so that reset will always be considered if configured

Author: Oron Port

compiler/stages/src/main/scala/dfhdl/compiler/stages/ToED.scala

@@ -260,8 +260,7 @@ case object ToED extends Stage:
                   clkCfg != None && (dclREGList.nonEmpty || processBlockAllMembers.nonEmpty && domainIsPureSequential)
 
                 if (hasSeqProcess)
-                  val dclREGsHaveRst = dclREGList.exists(_.hasNonBubbleInit)
-                  if (rstCfg != None && dclREGsHaveRst)
+                  if (rstCfg != None)
                     val RstCfg.Explicit(mode = mode) = rstCfg: @unchecked
                     mode match
                       case RstCfg.Mode.Sync =>

compiler/stages/src/test/scala/StagesSpec/ToEDSpec.scala

@@ -188,7 +188,10 @@ class ToEDSpec extends StageSpec(stageCreatesUnrefAnons = true):
          |    r := x + r
          |    y_din := r
          |  process(clk):
-         |    if (clk.actual.rising) y :== y_din
+         |    if (clk.actual.rising)
+         |      if (rst.actual == 1) {}
+         |      else y :== y_din
+         |    end if
          |end ID
          |
          |class IDTop extends EDDesign:
@@ -868,7 +871,10 @@ class ToEDSpec extends StageSpec(stageCreatesUnrefAnons = true):
          |  val rst = Rst_default <> IN
          |  val child = FooChild()
          |  process(clk):
-         |    if (clk.actual.rising) println(s"${child.y}")
+         |    if (clk.actual.rising)
+         |      if (rst.actual == 1) {}
+         |      else println(s"${child.y}")
+         |    end if
          |end Foo""".stripMargin
     )
   }