fix loop iterator printing in vhdl and also add test for verilog

Author: Oron Port

compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLOwnerPrinter.scala

@@ -131,9 +131,10 @@ protected trait VHDLOwnerPrinter extends AbstractOwnerPrinter:
     val dfValDcls =
       designMembers.view
         .flatMap {
+          case _ @IteratorDcl()        => None
           case p: DFVal.Dcl if p.isVar => Some(p)
           case _: DesignParam          => None
-          case c @ DclConst() =>
+          case c @ DclConst()          =>
             c.dfType match
               case DFInt32 => None
               case _       => Some(c)
@@ -214,7 +215,7 @@ protected trait VHDLOwnerPrinter extends AbstractOwnerPrinter:
     val dcl = csDFMembers(dcls).emptyOr(v => s"\n${v.hindent}")
     val named = pb.meta.nameOpt.map(n => s"$n : ").getOrElse("")
     val senList = pb.sensitivity match
-      case Sensitivity.All => " (all)"
+      case Sensitivity.All        => " (all)"
       case Sensitivity.List(refs) =>
         if (refs.isEmpty) "" else s" ${refs.map(_.refCodeString).mkStringBrackets}"
     s"${named}process$senList$dcl\nbegin\n${body.hindent}\nend process;"

compiler/stages/src/test/scala/StagesSpec/PrintVHDLCodeSpec.scala

@@ -20,7 +20,7 @@ class PrintVHDLCodeSpec extends StageSpec:
     val id1_y = SInt(16) <> VAR
     val id2_x = SInt(16) <> VAR
     val id2_y = SInt(16) <> VAR
-    val id1 = new ID:
+    val id1   = new ID:
       this.x <> id1_x
       this.y <> id1_y
     val id2 = new ID:
@@ -1306,4 +1306,55 @@ class PrintVHDLCodeSpec extends StageSpec:
          |end Foo_arch;""".stripMargin
     )
   }
+  test("for loop with a register printing") {
+    class Foo(
+        val PORT_WIDTH: Int <> CONST = 5
+    ) extends RTDesign:
+      val r = Bits(PORT_WIDTH) <> OUT.REG init all(0)
+      for (i <- 0 until PORT_WIDTH)
+        r(i).din := 1
+      for (i <- 0 until PORT_WIDTH)
+        if (r(PORT_WIDTH - 1 - i))
+          r(i).din := 0
+    end Foo
+    val top = (new Foo).getCompiledCodeString
+    assertNoDiff(
+      top,
+      """|library ieee;
+         |use ieee.std_logic_1164.all;
+         |use ieee.numeric_std.all;
+         |use work.dfhdl_pkg.all;
+         |use work.Foo_pkg.all;
+         |
+         |entity Foo is
+         |generic (
+         |  PORT_WIDTH : integer := 5
+         |);
+         |port (
+         |  clk : in std_logic;
+         |  rst : in std_logic;
+         |  r : out std_logic_vector(PORT_WIDTH - 1 downto 0)
+         |);
+         |end Foo;
+         |
+         |architecture Foo_arch of Foo is
+         |begin
+         |  process (clk)
+         |  begin
+         |    if rising_edge(clk) then
+         |      if rst = '1' then r <= repeat("0", PORT_WIDTH);
+         |      else
+         |        for i in 0 to PORT_WIDTH-1 loop
+         |          r(i) <= '1';
+         |        end loop;
+         |        for i in 0 to PORT_WIDTH-1 loop
+         |          if r((PORT_WIDTH - 1) - i) then r(i) <= '0';
+         |          end if;
+         |        end loop;
+         |      end if;
+         |    end if;
+         |  end process;
+         |end Foo_arch;""".stripMargin
+    )
+  }
 end PrintVHDLCodeSpec

compiler/stages/src/test/scala/StagesSpec/PrintVerilogCodeSpec.scala

@@ -22,7 +22,7 @@ class PrintVerilogCodeSpec extends StageSpec:
     val id1_y = SInt(16) <> VAR
     val id2_x = SInt(16) <> VAR
     val id2_y = SInt(16) <> VAR
-    val id1 = new ID:
+    val id1   = new ID:
       this.x  <> id1_x
       this.y  <> id1_y
       this.y2 <> OPEN
@@ -1221,4 +1221,43 @@ class PrintVerilogCodeSpec extends StageSpec:
          |endmodule""".stripMargin
     )
   }
+  test("for loop with a register printing") {
+    class Foo(
+        val PORT_WIDTH: Int <> CONST = 5
+    ) extends RTDesign:
+      val r = Bits(PORT_WIDTH) <> OUT.REG init all(0)
+      for (i <- 0 until PORT_WIDTH)
+        r(i).din := 1
+      for (i <- 0 until PORT_WIDTH)
+        if (r(PORT_WIDTH - 1 - i))
+          r(i).din := 0
+    end Foo
+    val top = (new Foo).getCompiledCodeString
+    assertNoDiff(
+      top,
+      """|`default_nettype none
+         |`timescale 1ns/1ps
+         |`include "Foo_defs.svh"
+         |
+         |module Foo#(parameter int PORT_WIDTH = 5)(
+         |  input  wire logic clk,
+         |  input  wire logic rst,
+         |  output logic [PORT_WIDTH - 1:0] r
+         |);
+         |  `include "dfhdl_defs.svh"
+         |  always_ff @(posedge clk)
+         |  begin
+         |    if (rst == 1'b1) r <= {PORT_WIDTH{1'b0}};
+         |    else begin
+         |      for (int i = 0; i < PORT_WIDTH; i = i + 1) begin
+         |        r[i] <= 1'b1;
+         |      end
+         |      for (int i = 0; i < PORT_WIDTH; i = i + 1) begin
+         |        if (r[(PORT_WIDTH - 1) - i]) r[i] <= 1'b0;
+         |      end
+         |    end
+         |  end
+         |endmodule""".stripMargin
+    )
+  }
 end PrintVerilogCodeSpec