fix verilog.v95/v2001 backend to use delays without time units and set the timescale according to the minimum.

Author: Oron Port

compiler/ir/src/main/scala/dfhdl/compiler/ir/DFType.scala

@@ -594,6 +594,15 @@ case object DFTime extends DFType.Companion[DFTime, (BigDecimal, DFTime.Unit)] w
         case `sec` => value * BigDecimal(1000000000000L)
         case `min` => value * BigDecimal(60000000000000L)
         case `hr`  => value * BigDecimal(3600000000000000L)
+    def to_basic_unit(value: BigDecimal): (BigDecimal, Unit) =
+      val psVal = to_ps(value)
+      if psVal < 1000 then (psVal, DFTime.Unit.ps)
+      else if psVal < 1000000 then (psVal / 1000, DFTime.Unit.ns)
+      else if psVal < 1000000000 then (psVal / 1000, DFTime.Unit.us)
+      else if psVal < 1000000000000L then (psVal / 1000000000L, DFTime.Unit.ms)
+      else (psVal / 1000000000000L, DFTime.Unit.sec)
+  end Unit
+end DFTime
 
 sealed trait DFFreq extends DFPhysical[DFFreq.Unit]
 case object DFFreq extends DFType.Companion[DFFreq, (BigDecimal, DFFreq.Unit)] with DFFreq:
@@ -610,9 +619,9 @@ case object DFFreq extends DFType.Companion[DFFreq, (BigDecimal, DFFreq.Unit)] w
       BigDecimal(1e12) / to_hz(value)
     def to_period(value: BigDecimal): (BigDecimal, DFTime.Unit) =
       val psVal = to_ps(value)
-      if psVal < BigDecimal(1000) then (psVal, DFTime.Unit.ps)
-      else if psVal < BigDecimal(1000000) then (psVal / 1000, DFTime.Unit.ns)
-      else if psVal < BigDecimal(1000000000) then (psVal / 1000, DFTime.Unit.us)
+      if psVal < 1000 then (psVal, DFTime.Unit.ps)
+      else if psVal < 1000000 then (psVal / 1000, DFTime.Unit.ns)
+      else if psVal < 1000000000 then (psVal / 1000, DFTime.Unit.us)
       else if psVal < 1000000000000L then (psVal / 1000000000L, DFTime.Unit.ms)
       else if psVal < 1000000000000000L then (psVal / 1000000000000L, DFTime.Unit.sec)
       else (psVal / 60000000000000L, DFTime.Unit.min)

compiler/ir/src/main/scala/dfhdl/compiler/printing/Printer.scala

@@ -155,7 +155,10 @@ trait Printer
   final def formatCode(cs: String, withColor: Boolean = printerOptions.color): String =
     val alignedContents = if (printerOptions.align) alignCode(cs) else cs
     if (withColor) colorCode(alignedContents) else alignedContents
+  private var currentDesign: Option[DFDesignBlock] = None
+  def getCurrentDesign: DFDesignBlock = currentDesign.get
   final def csFile(design: DFDesignBlock): String =
+    currentDesign = Some(design)
     val designDcl = design.instMode match
       case InstMode.Def => csDFDesignDefDcl(design)
       case _            => csDFDesignBlockDcl(design)

compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogDataPrinter.scala

@@ -85,13 +85,21 @@ protected trait VerilogDataPrinter extends AbstractDataPrinter:
     data match
       case Some(value) => value.toString
       case None        => "?"
+  val supportTimeUnits =
+    printer.dialect match
+      case VerilogDialect.v95 | VerilogDialect.v2001 => false
+      case _                                         => true
   def csDFTimeData(data: (BigDecimal, DFTime.Unit)): String =
-    val formattedValue = csBigDecimalData(data._1)
-    data._2 match
-      case DFTime.Unit.sec => s"${formattedValue}s"
-      case DFTime.Unit.min => printer.unsupported
-      case DFTime.Unit.hr  => printer.unsupported
-      case _               => s"${formattedValue}${data._2}"
+    if (supportTimeUnits)
+      val formattedValue = csBigDecimalData(data._1)
+      data._2 match
+        case DFTime.Unit.sec => s"${formattedValue}s"
+        case DFTime.Unit.min => printer.unsupported
+        case DFTime.Unit.hr  => printer.unsupported
+        case _               => s"${formattedValue}${data._2}"
+    else
+      val minTimeUnit = printer.minTimeUnitDesignMap(printer.getCurrentDesign)
+      csBigDecimalData(data._2.to_ps(data._1) / minTimeUnit.to_ps(1))
   def csDFFreqData(data: (BigDecimal, DFFreq.Unit)): String = printer.unsupported
   def csDFNumberData(data: (BigDecimal, DFNumber.Unit)): String = printer.unsupported
   def scalaToVerilogString(str: String): String =

compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogOwnerPrinter.scala

@@ -14,9 +14,18 @@ protected trait VerilogOwnerPrinter extends AbstractOwnerPrinter:
   def fileSuffix = "v"
   def defsName: String =
     s"${getSet.designDB.top.dclName}_defs"
-  def csLibrary(inSimulation: Boolean): String =
+  def csLibrary(inSimulation: Boolean, minTimeUnitOpt: Option[DFTime.Unit]): String =
+    val csTimeScale = minTimeUnitOpt.map { unit =>
+      def unitToStr(unit: DFTime.Unit): String =
+        unit match
+          case DFTime.Unit.sec => "s"
+          case _               => unit.toString
+      val scaleUnit = unitToStr(unit)
+      val precisionUnit = unitToStr(DFTime.Unit.ps.to_basic_unit(unit.to_ps(1e-3))._2)
+      s"`timescale 1${scaleUnit}/1${precisionUnit}"
+    }.getOrElse(s"`timescale 1ns/1ps")
     s"""`default_nettype none
-       |`timescale 1ns/1ps
+       |$csTimeScale
        |`include "${printer.globalFileName}"""".stripMargin
   def moduleName(design: DFDesignBlock): String = design.dclName
   val parameterizedModuleSupport: Boolean =
@@ -101,8 +110,22 @@ protected trait VerilogOwnerPrinter extends AbstractOwnerPrinter:
        |${statements.hindent}
        |endmodule""".stripMargin
   end csModuleDcl
+  lazy val minTimeUnitDesignMap = getSet.designDB.designMemberList.view.flatMap { (dsn, members) =>
+    val minTimePSOpt = members.view.collect {
+      case DFVal.Const(dfType = DFTime, data = (value: BigDecimal, unit: DFTime.Unit)) =>
+        unit.to_ps(value)
+    }.minOption
+    minTimePSOpt.map(ps => dsn -> DFTime.Unit.ps.to_basic_unit(ps)._2)
+  }.toMap
+  lazy val minTimeUnitGlobalOpt =
+    minTimeUnitDesignMap.values.view.map(_.to_ps(1)).minOption.map(ps =>
+      DFTime.Unit.ps.to_basic_unit(ps)._2
+    )
   def csDFDesignBlockDcl(design: DFDesignBlock): String =
-    s"""${csLibrary(design.inSimulation)}
+    // once there is a design with a set time unit, all designs must have a set time unit,
+    // so we can use the global time unit if the design does not have a set time unit
+    val minTimeUnitOpt = minTimeUnitDesignMap.get(design).orElse(minTimeUnitGlobalOpt)
+    s"""${csLibrary(design.inSimulation, minTimeUnitOpt)}
        |
        |${csModuleDcl(design)}
        |""".stripMargin

compiler/stages/src/test/scala/StagesSpec/PrintVerilogCodeSpec.scala

@@ -1016,7 +1016,7 @@ class PrintVerilogCodeSpec extends StageSpec:
          |        end
          |      end
          |    end
-         |    #10ns;
+         |    #10;
          |  end
          |endmodule""".stripMargin
     )