make sure iverilog knows the top-level

Oron Port · Oron Port · commit 5505f1131c4f · 2025-04-27T22:21:49.000+03:00
diff --git a/lib/src/main/scala/dfhdl/tools/toolsCore/IcarusVerilog.scala b/lib/src/main/scala/dfhdl/tools/toolsCore/IcarusVerilog.scala
@@ -40,6 +40,7 @@ object IcarusVerilog extends VerilogLinter, VerilogSimulator:
       ToolOptions,
       MemberGetSet
   ): String = constructCommand(
+    s"-s $topName",
     s"-o $topName"
   )
 

Original file line number	Diff line number	Diff line change
`@@ -40,6 +40,7 @@ object IcarusVerilog extends VerilogLinter, VerilogSimulator:`
`40`	`40`	`ToolOptions,`
`41`	`41`	`MemberGetSet`
`42`	`42`	`): String = constructCommand(`
	`43`	`+ s"-s $topName",`
`43`	`44`	`s"-o $topName"`
`44`	`45`	`)`
`45`	`46`