add 7seg resource

workaround scalac bug (not minimized)

Author: Oron Port

build.sbt

@@ -127,6 +127,7 @@ lazy val platforms = project
     libraryDependencies ++= commonDependencies
   )
   .dependsOn(
+    core % "test->test",
     lib
   )
 

internals/src/main/scala/dfhdl/internals/Exact.scala

@@ -294,13 +294,32 @@ private def exactOp2Macro[Op, Ctx, OutUB](
   import quotes.reflect.*
   val lhsExactInfo = lhs.exactInfo
   val rhsExactInfo = rhs.exactInfo
-  Expr.summonOrError[ExactOp2[
-    Op,
-    Ctx,
-    OutUB,
-    lhsExactInfo.Underlying,
-    rhsExactInfo.Underlying
-  ]] match
+  val exactOp2ExprOrError =
+    try
+      Expr.summonOrError[ExactOp2[
+        Op,
+        Ctx,
+        OutUB,
+        lhsExactInfo.Underlying,
+        rhsExactInfo.Underlying
+      ]]
+    catch
+      // TODO: this is a workaround for a Scala compiler bug that is not minimized yet.
+      // It throws an exception which somehow disappears when we widen the types and run show.
+      // Regression test is in platforms/src/test/scala/PlatformSpec.scala
+      case e: Throwable =>
+        lhsExactInfo.exactTpe.widen.show
+        rhsExactInfo.exactTpe.widen.show
+        Expr.summonOrError[ExactOp2[
+          Op,
+          Ctx,
+          OutUB,
+          lhsExactInfo.Underlying,
+          rhsExactInfo.Underlying
+        ]]
+    end try
+  end exactOp2ExprOrError
+  exactOp2ExprOrError match
     case Right(expr) => '{
         $expr(${ lhsExactInfo.exactExpr }, ${ rhsExactInfo.exactExpr })(using $ctx)
       }

lib/src/main/scala/dfhdl/platforms/resources/SevenSegDisplay.scala

@@ -0,0 +1,47 @@
+package dfhdl.platforms.resources
+import dfhdl.{DFC, Encoded}
+import dfhdl.hw.constraints.*
+import SevenSegDisplay.{Segment, Select}
+import dfhdl.compiler.ir.PhysicalNumber.Ops.us
+import dfhdl.compiler.ir.constraints.{IO, Timing}
+
+class SevenSegDisplay[L <: Int & Singleton](
+    val digits: L,
+    val selectActiveState: Select,
+    val segmentActiveState: Segment
+) extends ResourceGroup:
+  val SELECT = IOBus.fill(digits)(Select(selectActiveState))
+  val A = Segment(segmentActiveState)
+  val B = Segment(segmentActiveState)
+  val C = Segment(segmentActiveState)
+  val D = Segment(segmentActiveState)
+  val E = Segment(segmentActiveState)
+  val F = Segment(segmentActiveState)
+  val G = Segment(segmentActiveState)
+  val DP = Segment(segmentActiveState)
+end SevenSegDisplay
+object SevenSegDisplay:
+  enum Segment extends Encoded.Toggle:
+    case Off, On
+  object Segment:
+    @io(standard = io.Standard.LVCMOS, slewRate = io.SlewRate.SLOW)
+    @timing.ignore(maxFreqMinPeriod = 200.us)
+    protected[SevenSegDisplay] class Resource private[Segment] (val activeState: Segment)
+        extends ToggleIO[Segment]
+    protected[SevenSegDisplay] def apply(activeState: Segment)(using DFC): Resource =
+      new Resource(activeState)
+  enum Select extends Encoded.Toggle:
+    case Disabled, Enabled
+  object Select:
+    protected[SevenSegDisplay] class Resource private[Select] (val activeState: Select)
+        extends ToggleIO[Select]:
+      private val pullMode = if (activeState == Select.Enabled) IO.PullMode.DOWN else IO.PullMode.UP
+      injectConstraint(IO(
+        standard = IO.Standard.LVCMOS,
+        slewRate = IO.SlewRate.SLOW,
+        unusedPullMode = pullMode
+      ))
+      injectConstraint(Timing.Ignore(maxFreqMinPeriod = 200.us))
+    protected[SevenSegDisplay] def apply(activeState: Select)(using DFC): Resource =
+      new Resource(activeState)
+end SevenSegDisplay