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Oron Port
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add ApplyInvertConstraint stage and fix annotation ordering
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-7
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4 files changed

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‎compiler/stages/src/main/scala/dfhdl/compiler/stages/ApplyInvertConstraint.scala‎

Lines changed: 121 additions & 0 deletions
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@@ -0,0 +1,121 @@
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package dfhdl.compiler.stages
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import dfhdl.compiler.analysis.*
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import dfhdl.compiler.ir.*
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import dfhdl.compiler.patching.*
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import dfhdl.options.CompilerOptions
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import dfhdl.core.DFValAny
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import dfhdl.core.DFTypeAny
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import dfhdl.core.DFType.asFE
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import scala.collection.mutable
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import dfhdl.internals.BitVector
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/** This stage applies the invertActiveState constraint by inverting the port it's attached to. It
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* creates an intermediate variable called `{portName}_inverted` and connects it to the port.
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* - For output ports, the inverted intermediate variable is connected to the port.
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* - For input ports, the inverted input port is connected to the intermediate variable.
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* - All references to the port will point to the intermediate variable.
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* - The `invertActiveState` constraint is removed from the port.
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* For example,
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* ```
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* @io(invertActiveState = true)
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* val x1 = Bit <> IN
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* val y1 = Bit <> OUT
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* y1 <> x1
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* val x2 = Bit <> IN
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* @io(invertActiveState = true)
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* val y2 = Bit <> OUT
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* y2 <> x2
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* ```
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* will be transformed to
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* ```
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* val x1 = Bit <> IN
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* val x1_inverted = Bit <> VAR
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* x1_inverted <> !x1
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* val y1 = Bit <> OUT
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* y1 <> x1_inverted
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* val x2 = Bit <> IN
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* val y2 = Bit <> OUT
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* val y2_inverted = Bit <> VAR
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* y2 <> !y2_inverted
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* y2_inverted <> x2
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* ```
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*/
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case object ApplyInvertConstraint extends Stage:
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override def dependencies: List[Stage] = List()
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override def nullifies: Set[Stage] = Set()
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def transform(designDB: DB)(using getSet: MemberGetSet, co: CompilerOptions): DB =
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given RefGen = RefGen.fromGetSet
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val patchList: List[(DFMember, Patch)] = designDB.members.flatMap { member =>
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member match
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case dcl: DFVal.Dcl if dcl.isPort =>
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val invertBitSet = mutable.BitSet.empty
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// Check if this port has the invertActiveState constraint
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dcl.meta.annotations.foreach {
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case constraints.IO(bitIdx = bitIdx, invertActiveState = true) =>
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bitIdx match
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case bitIdx: Int => invertBitSet += bitIdx
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case _ => invertBitSet ++= (0 until dcl.width)
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case _ =>
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}
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if (invertBitSet.nonEmpty)
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val portName = dcl.getName
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val invertedVarName = s"${portName}_inverted"
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val updatedPortAnnots = dcl.meta.annotations.map {
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case ioConstraint: constraints.IO =>
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ioConstraint.copy(invertActiveState = None)
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case other => other
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}
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val updatedPortMeta = dcl.meta.copy(annotations = updatedPortAnnots)
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val updatedPort = dcl.copy(meta = updatedPortMeta)
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// Create a MetaDesign to add the new members
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val dsn = new MetaDesign(
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dcl,
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Patch.Add.Config.ReplaceWithMemberN(1, Patch.Replace.Config.ChangeRefAndRemove)
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):
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plantMember(updatedPort)
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// Create the inverted intermediate variable
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val inversionVar =
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dcl.dfType.asFE[DFTypeAny].<>(VAR)(using dfc.setName(invertedVarName))
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def invert(dfVal: DFValAny): DFValAny = dfVal.asIR.dfType match
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case _: DFBoolOrBit => !dfVal.asValOf[dfhdl.core.DFBit]
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case dfType: DFBits =>
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// all bits are inverted
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if (dfType.width == invertBitSet.size) ~dfVal.asValOf[dfhdl.core.DFBits[Int]]
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// otherwise, we need to use a mask
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else
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val maskStr =
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(for (i <- dfType.width - 1 to 0 by -1)
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yield
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if (invertBitSet.contains(i)) "1"
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else "0").mkString
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val mask = b"$maskStr"
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dfVal.asValOf[dfhdl.core.DFBits[Int]] ^ mask
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case _ => throw new RuntimeException(
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"Current implementation only supports constraint inversion for bits and booleans"
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)
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// Create the inversion and connection based on port direction
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if (dcl.isPortIn)
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inversionVar.asDclAny <> invert(updatedPort.asValAny)
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else
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updatedPort.asDclAny <> invert(inversionVar)
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List(
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dsn.patch
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)
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else Nil
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end if
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case _ => Nil
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}
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designDB.patch(patchList)
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end transform
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end ApplyInvertConstraint
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extension [T: HasDB](t: T)
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def applyInvertConstraint(using co: CompilerOptions): DB =
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StageRunner.run(ApplyInvertConstraint)(t.db)

‎compiler/stages/src/main/scala/dfhdl/compiler/stages/BackendPrepStage.scala‎

Lines changed: 24 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,29 @@ package dfhdl.compiler.stages
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case object BackendPrepStage
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extends BundleStage(
5-
DropUserOpaques, BreakOpsNoAssignments, DropUnreferencedAnons,
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NamedAnonMultiref, ExplicitRomVar, NamedVerilogSelection, NamedVHDLSelection,
7-
ToED, DropStructsVecs, MatchToIf, SimplifyMatchSel, DropDomains, DropMagnets,
5+
DropUserOpaques,
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BreakOpsNoAssignments,
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DropUnreferencedAnons,
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NamedAnonMultiref,
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ApplyInvertConstraint,
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ExplicitRomVar,
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NamedVerilogSelection,
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NamedVHDLSelection,
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ToED,
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DropStructsVecs,
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MatchToIf,
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SimplifyMatchSel,
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DropDomains,
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DropMagnets,
819
VHDLProcToVerilog,
9-
ExplicitNamedVars, DropLocalDcls, DropOutportRead, GlobalizePortVectorParams,
10-
LocalToDesignParams, DropDesignParamDeps, DropBAssignFromSeqProc, DropProcessAll,
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SimpleOrderMembers, ViaConnection
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ExplicitNamedVars,
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DropLocalDcls,
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DropOutportRead,
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GlobalizePortVectorParams,
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LocalToDesignParams,
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DropDesignParamDeps,
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DropBAssignFromSeqProc,
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DropProcessAll,
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SimpleOrderMembers,
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ViaConnection
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)

‎compiler/stages/src/test/scala/StagesSpec/ApplyInvertConstraintSpec.scala‎

Lines changed: 187 additions & 0 deletions
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package StagesSpec
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import dfhdl.*
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import dfhdl.compiler.stages.applyInvertConstraint
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import dfhdl.hw.constraints.io
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// scalafmt: { align.tokens = [{code = "<>"}, {code = "="}, {code = "=>"}, {code = ":="}]}
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class ApplyInvertConstraintSpec extends StageSpec:
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test("Basic input port inversion") {
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class ID extends RTDesign:
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@io(loc = "xloc", invertActiveState = true)
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val x = Bit <> IN
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val y = Bit <> OUT
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y <> x
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val id = (new ID).applyInvertConstraint
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assertCodeString(
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id,
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"""|class ID extends RTDesign:
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| @io(loc = "xloc")
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| val x = Bit <> IN
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| val x_inverted = Bit <> VAR
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| x_inverted <> (!x)
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| val y = Bit <> OUT
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| y <> x_inverted
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|end ID
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|""".stripMargin
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)
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}
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test("Basic output port inversion") {
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class ID extends RTDesign:
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val x = Bit <> IN
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@io(loc = "yloc", invertActiveState = true)
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val y = Bit <> OUT
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y <> x
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val id = (new ID).applyInvertConstraint
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assertCodeString(
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id,
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"""|class ID extends RTDesign:
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| val x = Bit <> IN
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| @io(loc = "yloc")
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| val y = Bit <> OUT
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| val y_inverted = Bit <> VAR
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| y <> (!y_inverted)
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| y_inverted <> x
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|end ID
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|""".stripMargin
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)
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}
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test("Both input and output ports inverted") {
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class ID extends RTDesign:
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@io(loc = "xloc", invertActiveState = true)
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val x = Bit <> IN
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@io(loc = "yloc", invertActiveState = true)
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val y = Bit <> OUT
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y <> x
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val id = (new ID).applyInvertConstraint
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assertCodeString(
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id,
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"""|class ID extends RTDesign:
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| @io(loc = "xloc")
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| val x = Bit <> IN
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| val x_inverted = Bit <> VAR
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| x_inverted <> (!x)
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| @io(loc = "yloc")
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| val y = Bit <> OUT
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| val y_inverted = Bit <> VAR
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| y <> (!y_inverted)
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| y_inverted <> x_inverted
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|end ID
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|""".stripMargin
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)
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}
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test("Bits type inversion using bitwise NOT") {
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class ID extends RTDesign:
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@io(bitIdx = 0, loc = "xloc0", invertActiveState = true)
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@io(bitIdx = 1, loc = "xloc1", invertActiveState = true)
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@io(bitIdx = 2, loc = "xloc2", invertActiveState = true)
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@io(bitIdx = 3, loc = "xloc3", invertActiveState = true)
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val x = Bits(4) <> IN
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val y = Bits(4) <> OUT
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y <> x
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val id = (new ID).applyInvertConstraint
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assertCodeString(
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id,
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"""|class ID extends RTDesign:
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| @io(bitIdx = 0, loc = "xloc0")
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| @io(bitIdx = 1, loc = "xloc1")
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| @io(bitIdx = 2, loc = "xloc2")
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| @io(bitIdx = 3, loc = "xloc3")
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| val x = Bits(4) <> IN
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| val x_inverted = Bits(4) <> VAR
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| x_inverted <> (~x)
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| val y = Bits(4) <> OUT
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| y <> x_inverted
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|end ID
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|""".stripMargin
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)
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}
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103+
test("Bits type inversion using bitwise NOT with mask") {
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class ID extends RTDesign:
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@io(bitIdx = 0, loc = "xloc0", invertActiveState = true)
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@io(bitIdx = 1, loc = "xloc1")
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@io(bitIdx = 2, loc = "xloc2")
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@io(bitIdx = 3, loc = "xloc3", invertActiveState = true)
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val x = Bits(4) <> IN
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val y = Bits(4) <> OUT
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y <> x
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val id = (new ID).applyInvertConstraint
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assertCodeString(
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id,
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"""|class ID extends RTDesign:
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| @io(bitIdx = 0, loc = "xloc0")
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| @io(bitIdx = 1, loc = "xloc1")
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| @io(bitIdx = 2, loc = "xloc2")
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| @io(bitIdx = 3, loc = "xloc3")
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| val x = Bits(4) <> IN
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| val x_inverted = Bits(4) <> VAR
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| x_inverted <> (x ^ h"9")
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| val y = Bits(4) <> OUT
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| y <> x_inverted
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|end ID
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|""".stripMargin
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)
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}
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test("Multiple ports with mixed inversion") {
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class ID extends RTDesign:
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@io(loc = "xloc1", invertActiveState = true)
133+
val x1 = Bit <> IN
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val y1 = Bit <> OUT
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@io(bitIdx = 0, loc = "xloc0", invertActiveState = false)
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@io(bitIdx = 1, loc = "xloc1", invertActiveState = true)
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@io(bitIdx = 2, loc = "xloc2", invertActiveState = true)
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@io(bitIdx = 3, loc = "xloc3", invertActiveState = true)
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val x2 = Bits(4) <> IN
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val y2 = Bits(4) <> OUT
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y1 <> x1
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y2 <> x2
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val id = (new ID).applyInvertConstraint
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assertCodeString(
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id,
146+
"""|class ID extends RTDesign:
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| @io(loc = "xloc1")
148+
| val x1 = Bit <> IN
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| val x1_inverted = Bit <> VAR
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| x1_inverted <> (!x1)
151+
| val y1 = Bit <> OUT
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| @io(bitIdx = 0, loc = "xloc0")
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| @io(bitIdx = 1, loc = "xloc1")
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| @io(bitIdx = 2, loc = "xloc2")
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| @io(bitIdx = 3, loc = "xloc3")
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| val x2 = Bits(4) <> IN
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| val x2_inverted = Bits(4) <> VAR
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| x2_inverted <> (x2 ^ h"e")
159+
| val y2 = Bits(4) <> OUT
160+
| y1 <> x1_inverted
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| y2 <> x2_inverted
162+
|end ID
163+
|""".stripMargin
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)
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}
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test("Double application has no effect") {
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class ID extends RTDesign:
169+
@io(loc = "xloc", invertActiveState = true)
170+
val x = Bit <> IN
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val y = Bit <> OUT
172+
y <> x
173+
val id = (new ID).applyInvertConstraint.applyInvertConstraint
174+
assertCodeString(
175+
id,
176+
"""|class ID extends RTDesign:
177+
| @io(loc = "xloc")
178+
| val x = Bit <> IN
179+
| val x_inverted = Bit <> VAR
180+
| x_inverted <> (!x)
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| val y = Bit <> OUT
182+
| y <> x_inverted
183+
|end ID
184+
|""".stripMargin
185+
)
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}
187+
end ApplyInvertConstraintSpec

‎plugin/src/main/scala/plugin/MetaContextGenPhase.scala‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,8 @@ class MetaContextGenPhase(setting: Setting) extends CommonPhase:
7373
val docOptTree = mkOptionString(docOpt)
7474
// the compiler does not transform the annotations, so we need to do it here.
7575
// See: https://github.com/scala/scala3/issues/23650
76-
val annotTree = mkList(annotations.map(a => transformAllDeep(a.tree)))
76+
// Also, we revesrse the annotations since for some reason the compiler reverses the order of the annotations.
77+
val annotTree = mkList(annotations.map(a => transformAllDeep(a.tree)).reverse)
7778
tree
7879
.select(setMetaSym)
7980
.appliedToArgs(

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