prevent compiling the code twice when printing the backend

Author: Oron Port

compiler/stages/src/main/scala/dfhdl/backends.scala

@@ -9,6 +9,11 @@ import dfhdl.compiler.stages.vhdl.{VHDLBackend, VHDLPrinter, VHDLDialect}
 import dfhdl.compiler.ir.DB
 object backends:
   protected[dfhdl] class verilog(val dialect: VerilogDialect) extends BackendCompiler:
+    def printer(
+        cd: CompiledDesign
+    )(using CompilerOptions, PrinterOptions): Printer =
+      val compiledDB = cd.stagedDB
+      new VerilogPrinter(dialect)(using compiledDB.getSet)
     def printer(
         designDB: DB
     )(using CompilerOptions, PrinterOptions): Printer =
@@ -24,6 +29,11 @@ object backends:
     val sv2017: verilog = new verilog(VerilogDialect.sv2017)
 
   protected[dfhdl] class vhdl(val dialect: VHDLDialect) extends BackendCompiler:
+    def printer(
+        cd: CompiledDesign
+    )(using CompilerOptions, PrinterOptions): Printer =
+      val compiledDB = cd.stagedDB
+      new VHDLPrinter(dialect)(using compiledDB.getSet)
     def printer(
         designDB: DB
     )(using CompilerOptions, PrinterOptions): Printer =

compiler/stages/src/main/scala/dfhdl/compiler/stages/BackendCompiler.scala

@@ -5,12 +5,17 @@ import dfhdl.options.{CompilerOptions, PrinterOptions}
 import dfhdl.compiler.printing.Printer
 import dfhdl.compiler.ir.DB
 
+//TODO: consider a way to combine the two printer methods into one,
+//without causing recompilation in DFApp when printing the backend code
 trait BackendCompiler:
   final def compile(
       sd: StagedDesign
   )(using co: CompilerOptions, po: PrinterOptions): CompiledDesign =
     CompiledDesign(sd.newStage(printer(sd.stagedDB).printedDB))
   end compile
+  def printer(
+      cd: CompiledDesign
+  )(using CompilerOptions, PrinterOptions): Printer
   def printer(
       designDB: DB
   )(using CompilerOptions, PrinterOptions): Printer

compiler/stages/src/main/scala/dfhdl/compiler/stages/CompiledDesign.scala

@@ -19,7 +19,7 @@ object CompiledDesign:
       import StagedDesign.transform as transform2
       CompiledDesign(staged.transform2(transformDB))
     def printBackendCode(using co: CompilerOptions, po: PrinterOptions): CompiledDesign =
-      Printer.printBackendCode(co.backend.printer(staged.stagedDB))
+      Printer.printBackendCode(co.backend.printer(cd))
       cd
     def commit(using co: CompilerOptions): CompiledDesign =
       cd.transform(designDB => Printer.commit(designDB, co.topCommitPath(designDB)))