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Oron Port
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fix global parameter usage detection
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compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogOwnerPrinter.scala

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -40,14 +40,16 @@ protected trait VerilogOwnerPrinter extends AbstractOwnerPrinter:
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lazy val globalUsage: Map[DFDesignBlock, Set[DFVal]] =
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val globalUsage = mutable.Map.empty[DFDesignBlock, Set[DFVal]]
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getSet.designDB.membersGlobals.foreach { m =>
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if (!m.isAnonymous) m.originMembersNoTypeRef.foreach {
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case o: DFVal.CanBeGlobal if !o.isGlobal =>
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val owner = o.getOwnerDesign
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globalUsage += owner -> (globalUsage.getOrElse(owner, Set()) + m)
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case _ =>
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}
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if (!m.isAnonymous)
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m.originMembersNoTypeRef.foreach {
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case o: DFVal.CanBeGlobal if o.isGlobal => // do not include global members
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case o =>
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val owner = o.getOwnerDesign
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globalUsage += owner -> (globalUsage.getOrElse(owner, Set()) + m)
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}
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}
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globalUsage.toMap
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end globalUsage
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def csModuleDcl(design: DFDesignBlock): String =
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val designMembers = design.members(MemberView.Folded)
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val ports = designMembers.view.collect { case p @ DclPort() =>

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