fix DFXInt width checking to useisSimilarTo instead of =~

Author: Oron Port

compiler/stages/src/test/scala/StagesSpec/PrintVerilogCodeSpec.scala

@@ -500,7 +500,7 @@ class PrintVerilogCodeSpec extends StageSpec:
     )
   test("UInt counter example"):
     class Counter(val width: Int <> CONST) extends RTDesign:
-      val cnt = UInt(width) <> OUT init d"8'0"
+      val cnt = UInt(width) <> OUT init 0
       cnt := cnt.reg + 1
     val top = (new Counter(8)).getCompiledCodeString
     assertNoDiff(

core/src/main/scala/dfhdl/core/DFDecimal.scala

@@ -719,7 +719,6 @@ object DFXInt:
       ): TC[DFXInt[LS, LW, LN], R] with
         type OutP = ic.OutP
         def conv(dfType: DFXInt[LS, LW, LN], value: R)(using dfc: DFC): Out =
-          import Ops.resize
           import DFUInt.Val.Ops.signed
           val rhs = ic(value)
           val (rhsSigned, rhsWidth) = rhs.getActualSignedWidth
@@ -811,9 +810,10 @@ object DFXInt:
                     lhsSignFix.toInt.asIR
                   case BitAccurate =>
                     DFVal.Alias.AsIs(dfType, lhsSignFix).asIR
-              else if (!(dfType.asIR.widthParamRef =~ lhsSignFix.dfType.asIR.widthParamRef))
+              else if (!dfType.asIR.widthParamRef.isSimilarTo(lhsSignFix.dfType.asIR.widthParamRef))
                 lhsSignFix.resize(dfType.widthIntParam).asIR
               else lhsSignFix.asIR
+              end if
             end if
           end dfValIR
           dfValIR.asValTP[DFXInt[RS, RW, RN], P]