@@ -37,22 +37,76 @@ trait VivadoSimCommon extends Linter, Simulator:
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protected def xsimFolder (using MemberGetSet ): String =
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s " xsim.dir ${separatorChar}work. ${topName}"
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+ private val workFolder = s " xsim.dir ${separatorChar}work "
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// TODO: check if the script is indeed shell script
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val axsimScript = if (osIsWindows) " axsim.bat" else " axsim.sh"
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- override protected [dfhdl] def producedFiles (using MemberGetSet , CompilerOptions ): List [String ] =
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+ // must clean up work folder when switching between verilog and vhdl backends
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+ private def cleanUp ()(using
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+ getSet : MemberGetSet ,
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+ co : CompilerOptions
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+ ): Unit =
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+ import java .nio .file .{Files , Paths , DirectoryStream }
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+ import scala .jdk .CollectionConverters ._
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+
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+ val dir = Paths .get(co.topCommitPath(topName)).resolve(workFolder)
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+ if (Files .exists(dir) && Files .isDirectory(dir))
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+ val removePattern = co.backend match
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+ case _ : backends.verilog => " *.vdb"
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+ case _ : backends.vhdl => " *.sdb"
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+ if (removePattern.nonEmpty)
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+ val stream : DirectoryStream [java.nio.file.Path ] =
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+ java.nio.file.Files .newDirectoryStream(dir, removePattern)
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+ try
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+ for (file <- stream.asScala)
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+ try Files .deleteIfExists(file)
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+ catch case _ : Throwable => ()
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+ finally
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+ stream.close()
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+ end cleanUp
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+
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+ override protected [dfhdl] def cleanUpBeforeFileRestore ()(using
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+ getSet : MemberGetSet ,
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+ co : CompilerOptions
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+ ): Unit = cleanUp()
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+
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+ override protected [dfhdl] def producedFiles (using
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+ getSet : MemberGetSet ,
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+ co : CompilerOptions
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+ ): List [String ] =
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val folder = xsimFolder
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val axsimRunExec = s " ${folder}${separatorChar}axsim ${if (osIsWindows) " .exe" else " " }"
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val xsimSuffixes = List (" dbg" , " mem" , " reloc" , " rtti" , " svtype" , " type" , " xdbg" )
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val xsimSupportFiles =
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xsimSuffixes.map(suffix => s " ${folder}${separatorChar}xsim. ${suffix}" )
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- axsimScript :: axsimRunExec :: xsimSupportFiles
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+ def compiledFilePath (dclName : String ): String =
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+ val name = co.backend match
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+ case _ : backends.vhdl => s " ${dclName.toLowerCase()}.vdb "
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+ case _ : backends.verilog =>
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+ dclName.flatMap { c =>
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+ if (c.isUpper) s " @ ${c.toLower}" else s " $c"
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+ } + " .sdb"
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+ s " ${workFolder}${separatorChar}${name}"
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+ def compiledVHDLPackageFiles : List [String ] =
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+ co.backend match
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+ case _ : backends.vhdl =>
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+ this .designDefFiles.map { path =>
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+ val fileName = path.split(separatorChar).last.toLowerCase()
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+ s " ${workFolder}${separatorChar}${fileName.replace(" .vhd" , " .vdb" )}"
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+ }
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+ case _ : backends.verilog => Nil
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+ val compiledFiles =
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+ s " $workFolder${separatorChar}work.rlx " :: compiledVHDLPackageFiles ++
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+ getSet.designDB.uniqueDesignMemberList.view.map(_._1.dclName).map(compiledFilePath).toList
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+ axsimScript :: axsimRunExec :: xsimSupportFiles ++ compiledFiles
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+ end producedFiles
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override protected [dfhdl] def simulatePreprocess (cd : CompiledDesign )(using
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co : CompilerOptions ,
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so : SimulatorOptions
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): CompiledDesign =
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+ cleanUp()(using cd.stagedDB.getSet)
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val ret = super .simulatePreprocess(cd)
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given MemberGetSet = ret.stagedDB.getSet
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val runExec = if (osIsWindows) " xelab.bat" else " xelab"
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