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Commit af1aebc

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Oron Port
committed
fix vivado caching and add cleanup mechanism for vivado work folder
1 parent 515018f commit af1aebc

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5 files changed

+67
-6
lines changed

5 files changed

+67
-6
lines changed

internals/src/main/scala/dfhdl/internals/DiskCache.scala

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@ class DiskCache(val cacheFolderStr: String):
7676
protected def cacheStrToValue(str: String): R
7777
protected def logCachedRun(): Unit = {}
7878
protected def runAfterValue(value: R): Unit = {}
79+
protected def cleanUpBeforeFileRestore(value: R): Unit = {}
7980
protected def genFiles(value: R): List[String] = Nil
8081
protected val name: String = typeName
8182
private lazy val keyHash: String =
@@ -99,7 +100,9 @@ class DiskCache(val cacheFolderStr: String):
99100
case Some(dataStr) =>
100101
logCachedRun()
101102
val value = cacheStrToValue(dataStr)
102-
if (hasGenFiles) restoreFiles(value)
103+
if (hasGenFiles)
104+
cleanUpBeforeFileRestore(value)
105+
restoreFiles(value)
103106
value
104107
case None =>
105108
put(name, "data", getDataHash, calcDataStr)

lib/src/main/scala/dfhdl/app/DFApp.scala

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -176,7 +176,8 @@ trait DFApp:
176176
hasGenFiles = true
177177
)(
178178
simulatorOptions.getTool.toString,
179-
simulatorOptions.getTool.installedVersion
179+
simulatorOptions.getTool.installedVersion,
180+
compilerOptions.backend.toString()
180181
):
181182
override protected def cacheEnable: Boolean = appOptions.cacheEnable
182183
override protected def genFiles(committed: CompiledDesign): List[String] =
@@ -185,6 +186,8 @@ trait DFApp:
185186
}
186187
protected def run(committed: CompiledDesign): CompiledDesign =
187188
committed.tap(_ => logger.info("Preparing external simulation...")).simPrep
189+
override protected def cleanUpBeforeFileRestore(committed: CompiledDesign): Unit =
190+
simulatorOptions.getTool.cleanUpBeforeFileRestore()(using committed.stagedDB.getSet)
188191
override protected def logCachedRun(): Unit =
189192
logger.info("Loading sim prep from cache...")
190193
protected def valueToCacheStr(value: CompiledDesign): String = value.stagedDB.toJsonString

lib/src/main/scala/dfhdl/tools/toolsCore/Tool.scala

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ trait Tool:
2828
protected def versionCmd: String
2929
protected def extractVersion(cmdRetStr: String): Option[String]
3030
protected[dfhdl] def producedFiles(using MemberGetSet, CompilerOptions): List[String] = Nil
31+
protected[dfhdl] def cleanUpBeforeFileRestore()(using MemberGetSet, CompilerOptions): Unit = {}
3132

3233
private[dfhdl] lazy val installedVersion: Option[String] =
3334
val getVersionFullCmd =

lib/src/main/scala/dfhdl/tools/toolsCore/VivadoSim.scala

Lines changed: 56 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,22 +37,76 @@ trait VivadoSimCommon extends Linter, Simulator:
3737

3838
protected def xsimFolder(using MemberGetSet): String =
3939
s"xsim.dir${separatorChar}work.${topName}"
40+
private val workFolder = s"xsim.dir${separatorChar}work"
4041

4142
// TODO: check if the script is indeed shell script
4243
val axsimScript = if (osIsWindows) "axsim.bat" else "axsim.sh"
4344

44-
override protected[dfhdl] def producedFiles(using MemberGetSet, CompilerOptions): List[String] =
45+
// must clean up work folder when switching between verilog and vhdl backends
46+
private def cleanUp()(using
47+
getSet: MemberGetSet,
48+
co: CompilerOptions
49+
): Unit =
50+
import java.nio.file.{Files, Paths, DirectoryStream}
51+
import scala.jdk.CollectionConverters._
52+
53+
val dir = Paths.get(co.topCommitPath(topName)).resolve(workFolder)
54+
if (Files.exists(dir) && Files.isDirectory(dir))
55+
val removePattern = co.backend match
56+
case _: backends.verilog => "*.vdb"
57+
case _: backends.vhdl => "*.sdb"
58+
if (removePattern.nonEmpty)
59+
val stream: DirectoryStream[java.nio.file.Path] =
60+
java.nio.file.Files.newDirectoryStream(dir, removePattern)
61+
try
62+
for (file <- stream.asScala)
63+
try Files.deleteIfExists(file)
64+
catch case _: Throwable => ()
65+
finally
66+
stream.close()
67+
end cleanUp
68+
69+
override protected[dfhdl] def cleanUpBeforeFileRestore()(using
70+
getSet: MemberGetSet,
71+
co: CompilerOptions
72+
): Unit = cleanUp()
73+
74+
override protected[dfhdl] def producedFiles(using
75+
getSet: MemberGetSet,
76+
co: CompilerOptions
77+
): List[String] =
4578
val folder = xsimFolder
4679
val axsimRunExec = s"${folder}${separatorChar}axsim${if (osIsWindows) ".exe" else ""}"
4780
val xsimSuffixes = List("dbg", "mem", "reloc", "rtti", "svtype", "type", "xdbg")
4881
val xsimSupportFiles =
4982
xsimSuffixes.map(suffix => s"${folder}${separatorChar}xsim.${suffix}")
50-
axsimScript :: axsimRunExec :: xsimSupportFiles
83+
def compiledFilePath(dclName: String): String =
84+
val name = co.backend match
85+
case _: backends.vhdl => s"${dclName.toLowerCase()}.vdb"
86+
case _: backends.verilog =>
87+
dclName.flatMap { c =>
88+
if (c.isUpper) s"@${c.toLower}" else s"$c"
89+
} + ".sdb"
90+
s"${workFolder}${separatorChar}${name}"
91+
def compiledVHDLPackageFiles: List[String] =
92+
co.backend match
93+
case _: backends.vhdl =>
94+
this.designDefFiles.map { path =>
95+
val fileName = path.split(separatorChar).last.toLowerCase()
96+
s"${workFolder}${separatorChar}${fileName.replace(".vhd", ".vdb")}"
97+
}
98+
case _: backends.verilog => Nil
99+
val compiledFiles =
100+
s"$workFolder${separatorChar}work.rlx" :: compiledVHDLPackageFiles ++
101+
getSet.designDB.uniqueDesignMemberList.view.map(_._1.dclName).map(compiledFilePath).toList
102+
axsimScript :: axsimRunExec :: xsimSupportFiles ++ compiledFiles
103+
end producedFiles
51104

52105
override protected[dfhdl] def simulatePreprocess(cd: CompiledDesign)(using
53106
co: CompilerOptions,
54107
so: SimulatorOptions
55108
): CompiledDesign =
109+
cleanUp()(using cd.stagedDB.getSet)
56110
val ret = super.simulatePreprocess(cd)
57111
given MemberGetSet = ret.stagedDB.getSet
58112
val runExec = if (osIsWindows) "xelab.bat" else "xelab"

project/DFHDLCommands.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -128,12 +128,12 @@ object DFHDLCommands {
128128
}
129129
//TODO: fix caching issues
130130
for (tool <- vhdlTools if existingTools.contains(tool); dialect <- vhdlDialects if !skip.contains((tool, dialect))) {
131-
val arguments = s" AES.top_CipherSim --nocache simulate -b $dialect -t $tool --Werror-tool"
131+
val arguments = s" AES.top_CipherSim simulate -b $dialect -t $tool --Werror-tool"
132132
val (updatedState, _) = extracted.runInputTask(runMainTask, arguments, newState)
133133
newState = updatedState
134134
}
135135
for (tool <- verilogTools if existingTools.contains(tool); dialect <- verilogDialects if !skip.contains((tool, dialect))) {
136-
val arguments = s" AES.top_CipherSim --nocache simulate -b $dialect -t $tool --Werror-tool"
136+
val arguments = s" AES.top_CipherSim simulate -b $dialect -t $tool --Werror-tool"
137137
val (updatedState, _) = extracted.runInputTask(runMainTask, arguments, newState)
138138
newState = updatedState
139139
}

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