fix: prevent missing domain location of internal designs inside top device design

Author: Oron Port

compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala

@@ -1091,6 +1091,7 @@ final case class DB(
         // Collect all location constraints to check for collisions
         val locationMap = mutable.Map.empty[String, String] // loc -> portName(idx)
         (design :: members).foreach {
+          case designInstance: DFDesignBlock if designInstance != design => // no need to check for location constraints in nested designs
           case domainOwner: DFDomainOwner =>
             domainOwner.domainType match
               case DomainType.RT(_) =>

lib/src/test/scala/ElaborationChecksSpec.scala

@@ -435,4 +435,28 @@ class ElaborationChecksSpec extends DesignSpec:
           |RHS:       y.resize(8)
           |Message:   Unexpected write access to the immutable value y.resize(8).""".stripMargin
     )
+  test("no need for clock location constraint check in internal designs"):
+    object Test:
+      import hw.constraints.*
+      class Internal extends RTDesign:
+        val x = Bit <> IN
+        val y = Bit <> OUT
+        y <> x.reg(1, init = 0)
+      end Internal
+      @deviceID(deviceID.Vendor.XilinxAMD, "test", "test", "")
+      @timing.clock(rate = 20.MHz)
+      @io(loc = "locClk")
+      @top(false) class Top extends RTDesign:
+        @io(loc = "locx")
+        val x = Bit <> IN
+        @io(loc = "locy")
+        val y = Bit <> OUT
+        val internal = Internal()
+        internal.x <> x
+        internal.y <> y
+    end Test
+    import Test.*
+    assertElaborationErrors(Top())(
+      "No error found"
+    )
 end ElaborationChecksSpec